Pentek 6210 Operating Manual page 44

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3.12 Processor Interface the HSP50214 DDR
'C6X Address
0x0032 0040
0x0032 0044
0x0032 0048
0x0032 004C
0x0032 0050 DDR Write Destination Address Register
0x0032 0054 DDR Read Source Register
0x0032 005C
The 6210's write interface to the HSP50214 uses an indirect addressing scheme
wherein a 32−bit data word is first loaded into four 8−bit master registers internal
to the DDR chip from the 8 LSB's of the four DDR Holding Registers on the 6210
(DDR0 − DDR3). The address of the desired destination register in the DDR is
then written to the 6210's DDR Write Destination Address Register (DDR4).
Writing this address triggers a circuit that generates a pulse, synchronous to a
clock, that loads the HSP 50214's internal Destination Register. The sync circuits
and data words are synchronized to different clocks (CLKIN or PROCCLK)
depending on the registers affected by a given write operation. For additional
information, you may refer to the
HSP50214 data
The 6210's read interface to the HSP50214 uses both read and write operations to obtain
data from the DDR. First, a 3−bit "read code" must be written must to the 6210's DDR
Read Source Register to select the source of data to be read. The data sources selected
by the various read codes are listed in
to the Read Source register will cause the 6210 to initiate a readout cycle, which will
transfer the requested data from the selected source to the 8 LSBs of some or all of the
6210's four DDR holding registers (DDR0 − DDR3), depending upon the specific data
source. For additional information, please refer to the
of the HSP50214 data
An additional register has been provided to allow the user to easily obtain status infor−
mation from the HSP50214. Reading the DDR Status Read Register (DDR6), will return
the status bits shown in
covered in the
Rev.: C
Table 3−14: Model 6210 − DDR Interface Resources
Register Description
DDR Holding Register 0
DDR Holding Register 1
DDR Holding Register 2
DDR Holding Register 3
DDR Status Read Register
sheet, in Appendix A
sheet, in Appendix A
Table 3−16, at the bottom of the next page. This topic is also
Read" section of
"Microprocessor
Pe n te k Mo del 6210 Ope rat ing Manual
(continued)
Mnemonic Access
DDR0 R/W
DDR1 R/W
DDR2 R/W
DDR3 R/W
DDR4 R/W
DDR5 R/W
DDR6 R. O.
Write" section of the
"Microprocessor
of this manual.
Table 3−15, at the top of the next page. Writing
"Microprocessor Read"
of this manual.
Appendix
Function
Control Word D0:D7
Control Word D8:D15
Control Word D16:D23
Control Word D24:D31
Control Register to Write
Source of Read Data
Status Register
section
A.