Pentek 6210 Operating Manual page 5

Pe nt e k Mo del 6210 Oper ating Manual
Table of Contents
Chapter 3: Memory Map and Register Descriptions
3.8 Data Format / Signal Path Register ...................................................................................................... 38
Table 3−9: Data Format / Signal Path Register ...........................................................................38
3.8.1 Decimate DDR Input by 2 ................................................................................................38
3.8.2 Pack Mode ..........................................................................................................................38
Table 3−10: Output Data to Motherboard BIFO − Packing Formats........................ 39
Table 3−11: A/D Output Data Coding .........................................................................40
3.8.3 Programmable−Gain Amplifier & Low−Pass Filter Bypass .......................................40
3.8.4 DDR Bypass........................................................................................................................41
3.9 SYNC Generate Register....................................................................................................................41
3.10 Serial Port 0 Connection Register .......................................................................................................... 42
Table 3−12: Serial Port 0 Connection Register............................................................................42
3.10.1 The Other Processor's Serial Port 0 Transmit Section ..................................................42
3.10.2 The Other Processor's DDR .............................................................................................42
3.10.3 The Processor's Own DDR ...............................................................................................42
3.10.4 Not Connected ...................................................................................................................43
3.11 CIC Gain Adjust Register ..................................................................................................................43
Table 3−13: CIC Gain Adjust Register .........................................................................................43
3.12 Processor Interface the HSP50214 DDR ..........................................................................................43
Table 3−14: DDR Interface Resources ..........................................................................................44
Table 3−15: DDR Read Source Definitions .................................................................................45
Table 3−16: DDR Status Read Register ........................................................................................45
Appendix A: Intersil HSP50214B − Programmable Downconverter
Appendix B: Analog Devices AD6640 − 12−Bit, 65 MSPS IF Sampling A/D Converter
Appendix C: Analog Devices AD603 − Variable Gain Amplifier
Appendix D: Linear Technology LTC1451 − 12−bit Rail to Rail DAC
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Rev.: C
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