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3.0
2.5
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.1
0.0
0.1
0.2
0.3
Figure 13. Gain Error for Cascaded Stages–Low Ripple
Mode
90
85
80
75
70
65
60
55
50
0
–0.2
0.2
Figure 14. ISNR vs. Control Voltage–Low Ripple Mode
C1
0.1 F
J1
RT
10V
1
100
R1
2.49k
+
C3
C4
2
0.1 F
100 F
NOTES
1
R
PROVIDES A 50
INPUT IMPEDANCE
T
2
C3 AND C5 ARE TANTALUM
REV. D
0.4
0.5
0.6
0.7
0.8 0.9
1.0 1.1
V
C
0.4
0.6
0.8
1.0
1.2
V
C
C7
10V
0.1 F
R13
2.49k
C2
0.1 F
A1
AD603
2.49k
R2
2.49k
+
C5
C6
2
0.1 F
100 F
1V OFFSET FOR
R5
SEQUENTIAL GAIN
5.49k
5.5V
1.05k
Figure 15. A Low Noise AGC Amplifier
THEORY OF THE AD603
A Low Noise AGC Amplifier
Figure 15 shows the ease with which the AD603 can be connected
as an AGC amplifier. The circuit illustrates many of the points
previously discussed: It uses few parts, has linear-in-dB gain,
operates from a single supply, uses two cascaded amplifiers in
sequential gain mode for maximum S/N ratio, and an external
resistor programs each amplifier's gain. It also uses a simple
temperature-compensated detector.
The circuit operates from a single 10 V supply. Resistors R1,
R2, R3, and R4 bias the common pins of A1 and A2 at 5 V.
This pin is a low impedance point and must have a low impedance
path to ground, here provided by the 100 µF tantalum capacitors
and the 0.1 µF ceramic capacitors.
The cascaded amplifiers operate in sequential gain. Here, the
offset voltage between the pins 2 (GNEG) of A1 and A2 is
1.05 V (42.14 dB × 25 mV/dB), provided by a voltage divider
consisting of resistors R5, R6, and R7. Using standard values,
the offset is not exact, but it is not critical for this application.
The gain of both A1 and A2 is programmed by resistors R13
and R14, respectively, to be about 42 dB; thus the maximum
gain of the circuit is twice that, or 84 dB. The gain-control
range can be shifted up by as much as 20 dB by appropriate
choices of R13 and R14.
The circuit operates as follows. A1 and A2 are cascaded. Capacitor
C1 and the 100 Ω of resistance at the input of A1 form a time-
constant of 10 µs. C2 blocks the small dc offset voltage at the
output of A1 (which might otherwise saturate A2 at its maxi-
mum gain) and introduces a high-pass corner at about 16 kHz,
eliminating low frequency noise.
A half-wave detector is used, based on Q1 and R8. The current
into capacitor C
current of Q2 (biased to be 300 µA at 300 K, 27°C) and the col-
lector current of Q1, which increases with the amplitude of the
THIS CAPACITOR SETS
AGC TIME CONSTANT
C8
10V
C
0.1 F
0.1 F
R14
2.49k
A2
10V
AD603
R3
R4
2.49k
AGC LINE
R7
3.48k
6.5V
R6
–9–
is just the difference between the collector
AV
10V
R9
R10
1.54k
1.24k
Q2
V
AGC
2N3906
R11
3.83k
AV
5V
Q1
2N3904
R12
4.99k
R8
806
C10
0.1 F
10V
AD603
C11
0.1 F
C9
0.1 F
J2
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