Pentek 6210 Operating Manual page 71

CONTROL WORD 9 BIT:
FORMAT
16
MSB = 0
SERIAL
OUT
16
MSB = 0
µP
(11 MANTISSA
4 EXPONENT)
26
IFIR
26
QFIR
†
Controlled via microprocessor interface.
Using AGC loop gain, the AGC range, and expected error
detector output, the gain adjustments per output sample for
the Loop Filter Section of the Digital AGC can be given by
(
AGC Slew Rate = 1.5dB THRESH
4
–
( ) 2 (
M
LG
3-23
TABLE 6C. AGC LIMIT DATA FORMAT
27 26 25
e e
AGC LOOP FILTER
M
U
X
LIMIT
EN
DET
AGC
LOAD
20
16 MANTISSA =
4
NNNN
EXP=2
01.XXXXXXXXXXXXXX
LIMIT
DET
18
18
AGC MULTIPLIER/SHIFTER
FIGURE 23. AGC BLOCK DIAGRAM
( ) ) ×
– MAG*1.64676
( )
– 15 E LG –
  (EQ. 18)
) 2
 
HSP50214B
24 23 22
e e m m
AGC ERROR SCALING
µP
(RANGE = -2.18344 TO 2.18344)
13
+
AGCGNSEL
†
UPPER LIMIT
†
LOWER LIMIT
18
IAGC
RESAMPLING
FIR FILTERS
LIMIT
AND
DET
INTERPOLATING
HALFBAND
FILTERS
18
QAGC
The loop gain determines the growth rate of the sum in the
loop accumulator which, in turn, determines how quickly the
AGC gain traces the transfer function given in Figures 21
and 22. Since the log of the gain response is roughly linear,
the loop response can be approximated by multiplying the
maximum AGC gain error by the loop gain. The expected
21 20 19 18
m m m m
DETECTOR
MANTISSA
EXP
4
4
MAGNITUDE
(RANGE = 0 TO 2.3)
(RANGE = 0 TO 1)
CARTESIAN
TO
POLAR
COORDINATE
CONVERTER
(G = 1.64676)
17 16
m m
AGC
ERROR
13
∆