Pentek 6210 Operating Manual page 4

Pag e 4
Table of Contents
2.4 Sync Bus − Serial I/O Connector
2.4.2 Serial Port Signals.............................................................................................................. 24
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.4
2.4.2.5
2.4.2.6
2.4.2.7
2.4.3 TTL−SYNC ......................................................................................................................... 25
2.5 Installing the Model 6210 on a VIM Motherboard ........................................................................ 26
2.5.1 Preparing the VIM Module for Installation................................................................... 26
Figure 2−6: VIM Module Countersunk Screws ........................................................ 26
Figure 2−7: VIM Module Nylon Spacer...................................................................... 27
2.5.2 Installing the VIM Module on the VIM Motherboard ................................................. 28
Figure 2−8: Model 4290 VIM Motherboard − Connectors & Mounting Holes ... 29
3.1 Overview ............................................................................................................................................. 31
3.2 Model 6210 Memory Map................................................................................................................. 31
Table 3−1: Model 6210 Memory Map ........................................................................................... 31
3.3 ID EEPROM Readout Register ............................................................................................................. 32
3.4 Control Register.................................................................................................................................. 32
Table 3−2: Control Register .......................................................................................................32
3.4.1 PROCCLK Frequency Divider ........................................................................................ 32
Table 3−3: Master PROCCCLK Signal Source & Frequency.................................. 33
3.4.2 BIFO Disable..................................................................................................................33
3.4.3 External Clock Enable....................................................................................................... 33
3.4.4 Termination Enable........................................................................................................... 33
3.4.5 Master / Slave.................................................................................................................... 34
3.5 Master Clock Divider......................................................................................................................... 34
Table 3−4: Master Clock Divider ..............................................................................................34
3.6 BIFO Decimation Register................................................................................................................. 35
Table 3−5: Motherboard BIFO Decimation Register ............................................................... 35
3.7 Programmable Gain Amplifier............................................................................................................. 36
Table 3−6: Programmable Gain Amplifier Register.................................................................. 36
3.7.1 Loading the 12−bit Gain Control Word ......................................................................... 36
Table 3−7: Gain Control Word vs. Full Scale Input Amplitude ............................ 37
Table 3−8: Sequence for Loading Gain Control Word ............................................ 37
Rev.: C
Chapter 2: Installation and Connections
(continued)
P0−CLKR1, P1−CLKR1................................................................................. 24
P0−FSR1, P1−FSR1 ........................................................................................ 24
P0−CLKS1, P1−CLKS1 .................................................................................. 24
P0−DR1, P1−DR1 ........................................................................................... 24
P0−CLKX1, P1−CLKX1................................................................................. 25
P0−FSX1, P1−FSX1 ........................................................................................ 25
P0−DX1, P1−DX1 ........................................................................................... 25
Chapter 3: Memory Map and Register Descriptions
Pe n te k Mo d el 6 2 1 0 O p e ra t i n g M a n u a l
(continued)
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