Pentek 6210 Operating Manual page 103

CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK)
BIT
POSITION FUNCTION
N/A Counter and
Accumulator Reset
3-55
HSP50214B
A write to this address initializes the counters and accumulators for testing. Items that are reset are:
Carrier NCO.
1. Loads phase offset <9:0> into register to be used for adding to accumulator.
2. Enables feedback on the accumulator.
CIC Filter
1. Resets the decimation counter.
2. Clears enables to CIC.
3. Clears accumulators in CIC.
4. Clears enable leaving CIC.
Halfband Filters
1. Resets compute counter in Halfband control.
2. Resets read address for all Halfband Filters.
3. Resets write address for all Halfband Filters.
4. Clears input available strobe.
5. Resets Halfband control logic.
255 Tap FIR
1. Resets FIR read and write address pointers.
2. Zero's coefficient read address.
AGC Loop
1. Clears accumulator in loop filter.
Re-Sampler and Interpolation Halfband Filters.
1. Resets counters for Halfband addresses for writing.
2. Resets output enable.
3. Reset controller for Re-Sampler.
Timing NCO
1. Initializes counters for inserting extra pulses when interpolating halfbands are enabled. In the
HSP50214B, a configuration control word bit determines if a Timing NCO reset is executed. If Con-
trol Word 27, Bit 20 is set to a logic one, a reset will clear the feedback in the timing NCO phase
accumulator. If Control Word 27, Bit 20 is zero, a reset will not clear the timing NCO phase accu-
mulator feedback, which is how the HSP50214 operated.
Discriminator
1. Resets read and write address pointers.
2. Zero's coefficient read address.
Cartesian to Polar Coordinate Counter
1. Resets Cordic counters (stops current computation).
FIFO Control
1. Resets decoder for controlling FIFO.
2. Resets write address for FIFO.
3. Clears RD and INTRRPT.
4. Resets "depth" and "full" flags.
5. Sets the empty flag.
6. Sets the read address to "7", write address to "0".
Snapshot Control
1. Zeros the group number.
2. Load interval counter.
3. Resets write address and read address for FIFO.
Output Serial Control
1. Reloads shift counter.
2. Reloads "Number of Words" counter.
3. Reloads counter for sync (for early or late).
4. Reloads counter for dividing down SERCLK.
5. In the HSP50214B, the Control Word 25 reset signal is designed such that the front end reset is 10
CLKIN periods wide and the back end reset is 10 PROCCLK periods wide. This guarantees that no
enables will be caught in the pipelines.
DESCRIPTION