Pentek 6210 Operating Manual page 16

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2.3 Model 6210 Front Panel Features
2.3.1
Rev.: C
External Clock Input
EXT CLK
0.1 F
50 Ω
Figure 2−3: Model 6210 − External Clock Input Circuit
2.3.1.1 Duty Cycle Sensitivity
Our experience with this device under different conditions, how−
ever, has not been quite so favorable. We have found that if the
device is operated at sample rates of 60 MHz or more, with an
input signal that is offset slightly from the sample rate (e. g., sam−
pling a 60.05 MHz signal at a 60 MHz sample rate), significant
conversion errors can occur at the ADC's output if the duty cycle
varies even marginally from 50%.
Referring to the AD6640's switching specifications for the
ENCODE input (this is where the sample clock signal is delivered),
we see that the minimum high and low pulse widths at that input
are both 6.5 nsec. Bearing that in mind, consider that a perfect
square wave at 65 MHz has a half−cycle time slightly less than
7.7 nsec. Now bring that perfect square wave into the real world,
where such things as rise and fall time exist, and you can see how
it might become difficult NOT to violate the 6.5 nsec pulse width
specification at the maximum sample rate.
There is a significant amount of signal conditioning and selection
circuitry between the 6210's EXT CLK input and the AD6640's
ENCODE input. This tends to cause a small amount of difference
between the duty cycle of the signal you deliver to the front panel
connector and the duty cycle of the signal we deliver to the ADC.
So, even if you know that your EXT CLK input signal has a duty
cycle of 50% + 0.00001%, that's probably not what the ADC sees.
Pe n te k Mo del 6210 Ope rat ing Manual
(continued)
(continued)
+ 3.3 V
1 kΩ
µ
50 Ω
1 kΩ
(continued)
10 kΩ
+
DS90LV032A
0.1 F µ
–
Clock
Select MUX
10 kΩ
To