Pentek 6210 Operating Manual page 122

AD6640
T1–1T
SINE
SOURCE
Figure 29. Sine Source – Differential Encode
If a low jitter ECL clock is available, another option is to ac-
couple a differential ECL signal to the encode input pins as
shown below. The capacitors shown here should be chip ca-
pacitors but do not need to be of the low inductance variety.
ECL
GATE
510 510
–V
S
Figure 30. Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
AD96687 (1/2)
50
510
–V
Figure 31. ECL Comparator for Encode
Driving the Analog Input
Because the AD6640 operates from a single +5 volt supply, the
analog input voltage range is offset from ground by 2.4 volt.
Each analog input connects through a 450 ohm resistor to the
2.4 volt bias voltage and to the input of a differential buffer
(Figure 32). This resistor network on the input properly biases
the followers for maximum linearity and range. Therefore, the
analog source driving the AD6640 should be ac-coupled to the
input pins. Since the differential input impedance of the AD6640
is 0.9 kΩ, the analog input power requirement is only –3 dBm,
simplifying the drive amplifier in many cases.
AIN
AIN
V
REF
0.1 F
0.01 F
Figure 32. Differential Analog Inputs
ENCODE
AD6640
R
ENCODE
0.1 F
ENCODE
AD6640
0.1 F
ENCODE
0.1 F
ENCODE
AD6640
0.1 F
ENCODE
510
S
BUF
AD6640
450
BUF
450
BUF
+2.4V
REFERENCE
To take full advantage of this high input impedance, a 20:1
transformer would be required. This is a large ratio and could
result in unsatisfactory performance. In this case, a lower
step-up ratio could be used. For example, if R
260 ohms, along with a 4:1 transformer, the input would match
to a 50 ohm source with a full-scale drive of +4 dBm (Figure
33). Note that the external load resistor, R
the AD6640 analog input resistance of 900 ohms. The external
resistor value can be calculated from the following equation:
where Z is the desired impedance (200 Ω for a 4:1 transformer
with 50 Ω input source).
ANALOG
INPUT
SIGNAL
0.1 F
Figure 33. Transformer-Coupled Analog Input Signal
If the lower drive power is attractive, a combination transformer
match and LC match could be employed that would use a 4:1
transformer with an LC as shown in Figure 34. This solution is
useful when good performance in the third Nyquist zone is
required. Such a requirement arises when digitizing high inter-
mediate frequencies in communications receivers.
ANALOG
+j100
SIGNAL
AT
–3dBm
–j125
Figure 34. Low Power Drive Circuit
In applications where gain is needed but dc-coupling is not
necessary, an extension of Figure 34 is recommended. A
50 ohm gain block may be placed in front of the LC matching
network. Such gain blocks are readily available for commercial
applications. These low cost modules can have excellent NF and
intermodulation performance. This circuit is especially good for
the "IF" receiver application previously mentioned.
In applications where dc-coupling is required the following
circuit can be used (Figure 35). It should be noted that the
addition of circuitry for dc-coupling may compromise performance
in terms of noise, offset and dynamic performance. This circuit
requires an inverting and noninverting signal path. Additionally,
an offset must be generated so that the analog input to each pin
is centered near 2.4 volts. Since the input is differential, small
differences in the dc voltage at each input can translate into an
offset for the circuit. The same holds true for gain mismatch.
Therefore, some means of adjusting the gain and offset between
–12–
were set to
T
, is in parallel with
T
1
=
R
T
1 1
–
Z 900
1:4
AIN
R
AD6640
T
AIN
V
REF
0.01 F
1:4
AIN
AD6640
AIN
V
REF
0.1 F
0.01 F
REV. 0