Pentek 6210 Operating Manual page 63

The phase of the Carrier NCO can be shifted by adding a
10-bit phase offset to the MSB's (modulo 360 o ) of the output
of the phase accumulator. This phase offset control has a
resolution of 0.35 o and can be interpreted as two's
complement from -180 o to 180 o
to 360 o
( )
0 to 2π . The phase offset is given by:
10 9
φ × ( ⁄ ) – ( (
= 2π PO 2 ; 2
OFF
– ( )
512 to 511
or, in terms of the parameter to be programmed:
10
[ ( φ ) 2π ⁄ ]
PO = INT 2
OFF HEX
where PO is the 10-bit two's complement value loaded into the
Phase Offset Register (Control Word 4, Bits 9-0). For example,
a value of 32 (decimal) loaded into the Phase Offset Register
would produce a phase offset of 11.25
would produce an offset of 180
the microprocessor interface. See the Microprocessor Write
Section on instructions for writing Control Word 4.
The most significant 18 bits from the phase adder are used
as the address a sin/cos lookup table. This lookup table
maps phase into sinusoidal amplitude. The sine and cosine
values have 18 bits of amplitude resolution. The spurious
components in the sine/cosine generation are at least
-102dBc. The sine and cosine samples are routed to the
mixer section where they are multiplied with the input
samples to translate the signal of interest to baseband.
The mixer multiplies the 14-bit input by the 18-bit quadrature
sinusoids. The mixer equations are:
× ( ω )
I = I cos
OUT IN c
× ( ω )
Q I sin
=
OUT IN c
The mixer output is rounded symmetrically to 15 bits.
To allow the frequency and phase of multiple parts to be
updated synchronously, two sets of registers are used for
latching the center frequency and phase offset words. The
offset phase and center frequency Control Words are first
loaded into holding registers. The contents of the holding
registers are transferred to active registers in one of two ways.
The first technique involves writing to a specific Control Word
Address. A processor write to Control Word 5, transfers the
center frequency value to the active register while a processor
write to Control Word 6 transfers the phase offset value to the
active register.
The second technique, designed for synchronizing updates to
multiple parts, uses the SYNCIN1 pin to update the active
registers. When Control Word 1, Bit 20 is set to 1, the SYNCIN1
pin causes both the center frequency and Phase Offset Holding
Registers to be transferred to active registers. Additionally,
when Control Word 0, Bit 0 is set to 1, the feedback in the
phase accumulator is zeroed when the transfer from the
holding to active register occurs. This feature provides
3-15
-π to π
( )
or as binary from 0
9
) PO ≤ ≤ ( ) )
2 – 1 (EQ. 4)
( π < φ < π )
; –
(EQ. 4A)
OFF
o
and a value of -512
o
. The phase offset is loaded via
(EQ. 5)
(EQ. 5A)
HSP50214B
synchronization of the phase accumulator starting phase of
multiple parts. It can also be used to reset the phase of the
NCO synchronous with a specific event.
The carrier offset frequency is loaded using the COF and
COFSYNC pins. Figure 13 details the timing relationship
between COF, COFSYNC and CLKIN. The offset frequency
word can be zeroed if it is not needed. Similarly, the
Sample Offset Frequency Register controlling the Re-
Sampler NCO is loaded via the SOF and SOFSYNC pins.
The procedure for loading data through the two pin NCO
interfaces is identical except that the timing of SOF and
SOFSYNC is relative to PROCCLK.
CLKIN
COFSYNC/
SOFSYNC
COF/
SOF
OTE: Data must be loaded MSB first.
IGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS
Each serial word has a programmable word width of either 8,
16, 24, or 32 bits (See Control Word 0, Bits 4 and 5, for the
Carrier NCO programming and Control Word 11, Bits 3 and
4, for Timing NCO programming). On the rising edge of the
clock, data on COF or SOF is clocked into an input shift
register. The beginning of a serial word is designated by
asserting either COFSYNC or SOFSYNC "high" one CLK
period prior to the first data bit.
†
32
30
28
26
†
24
22
20
18
†
16
14
12
10
†
8
6
4
2
0
2 6
†
Serial word width can be: 8, 16, 24, 32 bits wide.
†
T is determined by the COFSYNC, COFSYNC rate.
D
FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR
COF AND SOF SERIAL OFFSET FREQUENCY
DATA
NOTE: Serial Data must be loaded MSB first, and COFSYNC or
SOFSYNC should not be asserted for more than one
CLK cycle.
MSB
LSB
ASSERTION OF
COFSYNC, SOFSYNC
DATA TRANSFERRED
TO HOLDING REGISTER
(8)
(24) (32)
(16)
10 14 18 22 26 30 34 38
CLK TIMES
T
D
T
D
T
D
T
D
MSB
42 46 50 54
††
††
††
††