Pentek 6210 Operating Manual page 158

LTC1451
LTC1452/LTC1453
PI FU CTIO S
CLK: The TTL Level Input for the Serial Interface Clock.
D : The TTL Level Input for the Serial Interface Data. Data
IN
on the D pin is latched into the shift register on the rising
IN
edge of the serial clock.
CS/LD: The TTL Level Input for the Serial Interface Enable
and Load Control. When CS/LD is low the CLK signal is
enabled, so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
D : The Output of the Shift Register which Becomes
OUT
Valid on the Rising Edge of the Serial Clock.
BLOCK DIAGRA
CLK 1
D
2
IN
3
CS/LD
D
4
OUT
W U
TI I G DIAGRA
CLK
D
IN
PREVIOUS WORD
CS/LD
D
OUT
6
12-BIT
SHIFT
REGISTER
REGISTER
POWER-ON
RESET
W
t
t
2
1
t
9
B11
B0
MSB
B11
PREVIOUS WORD
GND: Ground.
REF: The Output of the Internal Reference and the Input
to the DAC Resistor Ladder. An external reference with
voltage up to V
V : The Buffered DAC Output.
OUT
: The Positive Supply Input. 4.5V ≤ V
V
CC
(LTC1451), 2.7 ≤ V
quires a bypass capacitor to ground.
LD
12-BIT DAC
DAC
REFERENCE
LTC1451: 2.048V
LTC1453: 1.22V
t
4
B10
t
8
B10
/2 may be used for the LTC1452.
CC
≤ 5.5V (LTC1452/LTC1453). Re-
CC
8 V
CC
+
V
7
OUT
–
6 REF
GND
5
11451/2/3 BD
t
6
t
3
B0
B1
LSB
t
5
B11
B1
B0
CURRENT WORD
≤ 5.5V
CC
t
7
1451/2/3 TD