Pentek 6210 Operating Manual page 96

BIT
POSITION FUNCTION
31 Reserved
30 Integration Mode
29-14 Integration Interval
13-0 Input Threshold
CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN)
BIT
POSITION FUNCTION
N/A Start Input Level
Detector AGC
Integrator
CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN)
BIT
POSITION FUNCTION
31-0 Carrier Center
Frequency
NOTE: In the HSP50214B, if the SYNCIN1 occurs when the NCO is not updating, the load signal is held internal to the part until the next NCO
update.
BIT
POSITION FUNCTION
31-10 Reserved
9-0 Carrier Phase Offset
CONTROL WORD 5: CARRIER FREQUENCY STROBE (SYNCHRONIZED TO CLKIN)
BIT
POSITION FUNCTION
N/A Carrier Frequency
Strobe
BIT
POSITION FUNCTION
N/A Carrier Phase Strobe
3-48
CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN)
Reserved.
0- Integration of magnitude error stops when the interval counter times out.
1- Integration runs continuously. When the interval counter times out, the integrator reloads, and the re-
sults of the integration is sent to a register for the processor to read.
These are the top 16 bits of the 18-bit integration counter, ICPrel. ICPrel = (N)/4+1; where N is the de-
sired integration period in CLKIN cycles, defined as the number of input samples to be integrated. N must
be a multiple of 4: [0, 4, 8, 12, 16.... , 2
must be accounted for, as they will be added to the threshold! If the gated input mode is used, the same
input sample will be accumulated multiple times.
Input Magnitude Threshold. Bits 12-0 correspond to input bits 12-0. The magnitude of the input is added
to this threshold, where the threshold is a signed number. Bit 13 is the MSB.
Writing to this location starts/restarts the input AGC error integrator. The integrator will either restart or
stop when the integration interval counter times out depending on bit 30 of Control Register 1 (see Mi-
croprocessor Write Section).
These bits control the frequency of the Carrier NCO. The frequency range of the NCO is ± f
f is the input sample rate. The bits are computed by the equation N = (F
S
This location is a holding register. After loading, a transfer to the active register is done by writing to Con-
trol Word 5 or by generating a SYNCIN1 with Control Word 0, Bit 20 set to 1. The Carrier NCO only up-
dates ENI is active.
CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN)
Reserved.
These bits, PO, are used to offset the phase of the carrier NCO. The bits are computed by the Equation
10 φ
PO = INT[(2 )/ 2π]
off
bit offset binary representation. Bit 9 is the MSB. This location is a holding register. After loading, a trans-
fer to the active register is done by writing to Control Word 6 or by generating a SYNCIN1 with Control
Word 0, Bit 20 set to 1. The carrier NCO only updates when ENI is active.
Writing to this address updates the carrier frequency Control Word from the Holding Register.
CONTROL WORD 6: CARRIER PHASE STROBE (SYNCHRONIZED TO CLKIN)
Writing to this address updates the carrier phase offset Control Word with the value written to the phase
offset (PO) register.
HSP50214B
DESCRIPTION
18
]. Bit 29 is the MSB. If the input is interpolated, then the zeros
DESCRIPTION
DESCRIPTION
DESCRIPTION
< π) for 10-bit 2's complement representation or from 0 to 2π for 10-
; (-π <φ
HEX off
DESCRIPTION
DESCRIPTION
/2 where
S
32
/ f )*2 . Bit 31 is the MSB.
NCO S