Pentek 6210 Operating Manual page 97

CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK)
BIT
POSITION FUNCTION
31-22 Reserved
21 Enable External
Filter Sync
20 Halfband (HB)
Bypass
19 HB5 Enable
18 HB4 Enable
17 HB3 Enable
16 HB2 Enable
15 HB1 Enable
14-11 FIR Decimation
10 FIR Real/Complex
9 FIR Sym Type
8 FIR Symmetry
7-0 FIR Taps
CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK)
BIT
POSITION FUNCTION
31-30 Reserved
29 Sync AGC Updates to
SYNCIN2
28-16 Threshold
15-12 Loop Gain 1
Mantissa
11-8 Loop Gain 1
Exponent
7-4 Loop Gain 0 Mantissa
3-0 Loop Gain 0
Exponent
3-49
HSP50214B
Reserved.
0- The SYNCIN2 pin has no effect on the halfband and FIR filters.
1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR, the res-
ampler, and the discriminator are reset. SYNCIN2 can be used to synchronize the computations of the
filters in multiple parts for the alignment (see Synchronization Section).
1- Bypass Halfband Filters.
0- Enable HB Filters (at least one HB must be enabled).
0- Disables HB number 5 (the last in the cascade).
1- Enables HB filter number 5.
Setting this bit enables HB filter number 4.
Setting this bit enables HB filter number 3.
Setting this bit enables HB filter number 2.
Setting this bit enables HB filter number 1.
Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB.
0001 - 1 1001 - 9
0010 - 2 1010 - 10
0011 - 3 1011 - 11
0100 - 4 1100 - 12
0101 - 5 1101 - 13
0110 - 6 1110 - 14
0111 - 7 1111 - 15
1000 - 8 0000 - 16
0- Complex Filter.
1- Dual Real Filters.
0- Odd Symmetry.
1- Even Symmetry.
0- Symmetric Filters.
1- Asymmetric Filters.
Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid.
Reserved.
When this bit is 1, the SYNCIN2 pin loads the contents of the master registers into the AGC accumulator.
The magnitude measurement out of the cartesian to polar converter is subtracted from this value to get
the gain error. A gain of 1.647 in the cartesian to polar conversion that must be taken into account when
computing this threshold. These bits are weighted -2
Selected when AGCGNSEL = 1. These bits, MMMM, together with the exponent bits, EEEE (11-8), set
the loop gain for the AGC loop. The gain adjustment per output sample is:
1.5dB (Threshold -[Magnitude * 1.6]) 0.MMMM * 2
and the threshold is programmed in bits 28-16. The decimal value for the mantissa is calculated as
DEC(MMMM)/16. Bit 15 is the MSB.
Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is the MSB.
Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same equations
are used for Loop 0. Bit 7 is the MSB.
Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same equations
are used for Loop 0. Bit 3 is the MSB.
DESCRIPTION
DESCRIPTION
2 -10
down to 2 . Bit 28 is the MSB.
-(15 - EEEE)
where magnitude ranges from 0 to 1.414