Pentek 6210 Operating Manual page 112

AD6640–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
1
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
POWER SUPPLY REJECTION (PSRR)
2
REFERENCE OUT (V )
REF
ANALOG INPUTS (AIN, AIN)
Analog Input Common-Mode Range
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
Supply Voltage
AV
CC
DV
CC
Supply Current
IA (AV = 5.0 V)
VCC CC
ID (DV = 3.3 V)
VCC CC
POWER CONSUMPTION
NOTES
1
ENCODE = 20 MSPS
2
If V is used to provide a dc offset to other circuits, it should first be buffered.
REF
3 The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels V
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4
Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
Specifications subject to change without notice
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS (ENC, ENC)
Encode Input Common-Mode Range
Differential Input Voltage
Single-Ended Encode
3
Logic Compatibility
Logic "1" Voltage
Logic "0" Voltage
Logic "1" Current (V = 5 V)
INH
Logic "0" Current (V = 0 V)
INL
Input Capacitance
LOGIC OUTPUTS (D11–D0)
Logic Compatibility
Logic "1" Voltage (DV = +3.3 V)
CC
Logic "0" Voltage (DV = +3.3 V)
CC
Logic "1" Voltage (DV = +5.0 V)
CC
Logic "0" Voltage (DV = +5.0 V)
CC
Output Coding
NOTES
Best dynamic performance is obtained by driving ENC and ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is
1
shown in Figure 18 under Typical Performance Characteristics.
2
For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the
input voltage on either encode pin does not go below 0 V. The maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AV
for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).
3 ENC or ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sources
will work. When driving only one encode input, bypass the complementary input to GND with 0.01 µF.
4
Digital output load is one LCX gate.
Specifications subject to change without notice.
(AV = +5 V, DV = +3.3 V; T
CC CC
Temp
+25°C
Full
Full
1
+25°C
Full
Full
Full
Full
Full
3
4
Full
Full
Full
+25°C
Full
Full
Full
Full
Full
.
(AV = +5 V, DV
CC CC
Temp
1
2
Full
Full
Full
Full
Full
Full
+25°C
4
Full
Full
Full
Full
= –40 C, T = +85 C)
MIN MAX
Test
Level Min
I
VI –10
VI –10
I –1.0
V
V
V
V
V
V
V
IV 0.7
V
VI 4.75
VI 3.0
VI
VI
VI
± 0.5 volts. The input signals should be 180 degrees out of phase to
REF
= +3.3 V; T = –40 C, T = +85 C)
MIN MAX
Test
Level Min
IV 0.2
IV 0.4
VI 2.0
VI 0
VI 500
VI –400
V
VI 2.8
VI
IV 4.5
IV
Twos Complement
–2–
AD6640AST
Typ Max
12
GUARANTEED
3.5 +10
4.0 +10
± 0.5
+1.5
± 1.25
50
100
± 0.5
2.4
± 0.05
V
REF
2.0
0.9 1.1
1.5
5.0 5.25
3.3 5.25
135 160
10 20
710 865
AD6640AST
Typ Max
2.2
10
TTL/CMOS
5.0
0.8
650 800
–320 –200
2.5
CMOS
DV – 0.2
CC
0.2 0.5
DV – 0.3
CC
0.35 0.5
Units
Bits
mV
% FS
LSB
LSB
ppm/°C
ppm/°C
mV/V
V
V
V p-p
kΩ
pF
V
V
mA
mA
mW
Units
V
V p-p
V p-p
V
V
µA
µA
pF
V
V
V
V
(e.g.,
CC
REV. 0