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Pentek 6210 Operating Manual

Pentek dual a/d converter and digital receiver vim module for pentek vim motherboards
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Pe nt e k Mo del 6210 Oper ating Manual
P age 1
OPERATING MANUAL
PENTEK MODEL 6210
Dual A/D Converter and Digital Receiver
VIM Module for Pentek VIM Motherboards
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
(201) 818−5900
http://www.pentek.com/
Copyright © 1998 − 2001
Manual Part #: 800.62100
Rev.: C − April 5, 2001

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  • Page 1 Pe nt e k Mo del 6210 Oper ating Manual P age 1 OPERATING MANUAL PENTEK MODEL 6210 Dual A/D Converter and Digital Receiver VIM Module for Pentek VIM Motherboards Pentek, Inc. One Park Way Upper Saddle River, NJ 07458 (201) 818−5900...

  • Page 2: Copyright Information

    The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product which in Pentek’s sole opinion proves to be defective within the scope of the warranty.

  • Page 3: Table Of Contents

    Chapter 2: Installation and Connections Inspection.............................13 Jumper Blocks............................13 Table 2−1: Factory Jumper Settings....................13 Figure 2−1: Model 6210 PC Board, Showing Jumper Blocks & Mounting Holes ....14 2.2.1 External Clock Function Select Jumper ................13 Table 2−2: External Clock ....................13 Model 6210 Front Panel Features .....................15 Figure 2−2: Model 6210 Front Panel ....................15...
  • Page 4 2.4.2.7 P0−DX1, P1−DX1 ................... 25 2.4.3 TTL−SYNC ......................... 25 Installing the Model 6210 on a VIM Motherboard ................ 26 2.5.1 Preparing the VIM Module for Installation..............26 Figure 2−6: VIM Module Countersunk Screws ............26 Figure 2−7: VIM Module Nylon Spacer..............27 2.5.2...
  • Page 5 Pe nt e k Mo del 6210 Oper ating Manual P age 5 Table of Contents Page Chapter 3: Memory Map and Register Descriptions (continued) Data Format / Signal Path Register ...................... 38 Table 3−9: Data Format / Signal Path Register ................38 3.8.1...
  • Page 6 Introduction ............................. E−1 Table E−1: VIM ID EEPROM Register ..................E−1 EEPROM Format Example ......................E−1 Table E−2: EEPROM Example (Model 6210 shown) .............. E−2 Appendix F: Application Note Introduction ............................. F−1 Figure F−1: HSP50214 Simplified Block Diagram ..............F−1 Output Sample Rate and Bandwidth Specifications..............

  • Page 7: Chapter 1: Overview

    Chapter 1: Overview General Description Pentek’s Model 6210 is a VIM−2 Digital Drop Receiver (DDR) module (devices of this type are also often referred to as Digital Down Converters, or DDCs), designed to be attached directly to any of Pentek’s DSP− or RISC−based VIM motherboards, such as Pentek Models 4290, 4291 and 4292.

  • Page 8: A/D Converters

    Connection to VIM Motherboard Both 16−bit parallel output data ports (ports A and B) from the Model 6210 flow into the FIFO structures on the VIM motherboard. A control path from each motherboard processor permits direct programming of the HSP50214B functions including tuning, decimation, output formatting, filter control and filter coefficients.

  • Page 9: Simplified Block Diagram

    Pe nt e k Mo del 6210 Oper ating Manual P age 9 Simplified Block Diagram Figure 1−1, below, provides a simplified block diagram of the Model 6210. Sample Clock RF In RF In In/Out 64 MHz Crystal Oscillator Programmable...

  • Page 10: Specifications

    Page 1 0 Pe n te k Mo del 6210 Ope rat ing Manual Specifications The specifications below are typical, at 25°C ambient temperature, with + 5 V and ± 12 V power supplies within ± 1 % of nominal, unless otherwise specified.
  • Page 11 Pe nt e k Mo del 6210 Oper ating Manual P age 11 Specifications (continued) Signal Purity Front End Performance w/ Programmable Amp Harmonic Distortion: −60 dB Signal/Noise Ratio (30 MHz) −50 dB Spur Free Dynamic Range: −65 dB Crosstalk: −60 dB @ 1 MHz...
  • Page 12 Page 1 2 Pe n te k Mo del 6210 Ope rat ing Manual Specifications (continued) Power Requirements: +5 V Min. (idle): 760 mA Max. (loaded): 2000 mA +12 V Min. (idle): 750 mA Max. (loaded): 750 mA −12 V Min.

  • Page 13: Chapter 2: Installation And Connections

    Pe nt e k Mo del 6210 Oper ating Manual P age 13 Chapter 2: Installation and Connections Inspection After unpacking the unit, inspect it carefully for possible damage to connectors or components. If any damage is discovered, please contact Pentek immediately at (201) 818−5900.
  • Page 14 Page 1 4 Pe n te k Mo del 6210 Ope rat ing Manual B a s e b o a rd M ou n tin g H o le s (a) Component Side B a s e b o a rd M o u n tin g H o le s...

  • Page 15: Model 6210 Front Panel Features

    6210’s A/D converters, or as the reference clock signal for its DDR. The External Clock Input circuit used on Pentek's Model 6210 is designed to accept Low−Voltage Differential Signals (LVDS). The impedance presented by the external clock input is 50 Ω...
  • Page 16 Page 1 6 Pe n te k Mo del 6210 Ope rat ing Manual Model 6210 Front Panel Features (continued) 2.3.1 External Clock Input (continued) + 3.3 V 10 kΩ 1 kΩ EXT CLK 0.1 F µ 50 Ω DS90LV032A 50 Ω...

  • Page 17: Analog Inputs − Ch1 In, Ch2 In

    The other eight are general purpose indicators controlled by the processors on the VIM motherboard, and are visible through the cutouts at the left side of the 6210’s front panel. These will all be discussed in the sub− sections that begin at the top of the next page.

  • Page 18: Sync Bus Master Led − Mas

    The red TRM LED, the rightmost one near the panel’s center, indi− cates that the Sync Bus Master termination has been enabled for the 6210 in question. This means that the 6210 on whose panel this LED is lit will be the one that provides the terminating resistors for the Sync signals generated by the Sync Bus master.

  • Page 19: Sync Bus − Serial I/O Connector

    Ground P1−FSX1 P1−DX1 Up to eight (8) 6210’s can be operated synchronously by cabling these connec− tors together. Further details about how this is accomplished are provided in the subsections beginning on the page after next, and in Sections 3.4 and 3.9.
  • Page 20 (Control Reg., D2) 64 MHz Oscillator Figure 2−5: Model 6210 − Block Diagram of Clock and Sync Signal Sources DDR 1 is controlled by VIM Motherboard Processor A or C, and DDR2 is controlled by Note Processor B or D, depending where the VIM module is installed on the motherboard.

  • Page 21: Mclk, Mclk

    This signal is used as both the sample clock for the A/D con− verters, and the front−end processing clock for the DDRs. When the Model 6210 is configured as a master, this is an LVDS output at the A/D sample clock rate. If the board is configured for an external clock, then the original source for this signal is the EXT CLK SMA input connector.

  • Page 22: Msync, Msync

    (or the falling edge of the nor− mally−high SYNC1). If the Model 6210 is configured as a Sync bus master, this is a dif− ferential LVDS output. SYNC OUT of Channel 2’s HSP50214B DDR is used as the source for the differential LVDS output. For proper operation, the Syncout CLK Select bit (D3) of DDR2’s Con−...

  • Page 23: Sync2, Sync2

    At the time of this manual’s publication, Pentek manufactures four devices that use the same physical connector to implement a Sync bus and Serial I/O port. These are the Models 6210 and 6216 Dig− ital Reciver/ADCs, the Model 6211 A/D Converter, and the Model 6229 Digital Transmitter/DAC.

  • Page 24: Serial Port Signals

    Processors A & B on the VIM motherboard, then Processor A’s serial port 1 is P0, and Processor B’s serial port 1 is P1. If the Model 6210 is installed above VIM motherboard Processors C & D, then Processor C’s serial port 1 is P0, and Processor D’s serial port 1 is P1.

  • Page 25: P0−Clkx1, P1−Clkx1

    Pe nt e k Mo del 6210 Oper ating Manual P age 25 Sync Bus − Serial I/O Connector (continued) 2.4.2 Serial Port Signals (continued) 2.4.2.5 P0−CLKX1, P1−CLKX1 These are the Serial Port Transmit Clock signals from the VIM motherboard.

  • Page 26: Installing The Model 6210 On A Vim Motherboard

    Installing the Model 6210 on a VIM Motherboard Pentek’s VIM motherboard ship with two blank panels where optional VIM modules, such as the Model 6210, can be installed. This section provides directions for removing blank panels, and installing the Model 6210, or other VIM modules.

  • Page 27: Figure 2−7: Vim Module Nylon Spacer

    Pe nt e k Mo del 6210 Oper ating Manual P age 27 Installing the Model 6210 on a VIM Motherboard (continued) 2.5.1 Preparing the VIM Module for Installation (continued) 3) Remove the two shipping brackets that were used to mount the front panel to the VIM module, by removing the two pan−head Phillips screws...

  • Page 28: Installing The Vim Module On The Vim Motherboard

    Page 2 8 Pe n te k Mo del 6210 Ope rat ing Manual Installing the Model 6210 on a VIM Motherboard (continued) 2.5.2 Installing the VIM Module on the VIM Motherboard 1) With the VIM motherboard’s component side (the one with the mezzanine...

  • Page 29: Figure 2−8: Model 4290 Vim Motherboard − Connectors & Mounting Holes

    Pe nt e k Mo del 6210 Oper ating Manual P age 29 Ejector Handle Screw Ejector Handle Screw Slotted Screw Slotted Screw 'C6x A Top Position Mounting Holes 'C6x B 'C6x C Bottom Position Mounting Holes 'C6x D Ejector Handle Screw Slotted Screw Figure 2−8: Model 4290 VIM Motherboard −...
  • Page 30 Page 3 0 Pe n te k Mo del 6210 Ope rat ing Manual This page is intentionally blank Rev.: C...

  • Page 31: Chapter 3: Memory Map And Register Descriptions

    Chapter 3: Memory Map and Register Descriptions Overview This section covers access to the Model 6210 from the VIM motherboard. Memory maps to VIM module resources are given from the motherboard processor’s viewpoint, and details are provided describing the use of each resource.

  • Page 32: Id Eeprom Readout Register

    Control Register − R/W @ ‘C6x Address 0x0032 0020 The Control Register allows you to configure the Model 6210 as a master or slave on the sync bus and to toggle the on−board sync bus termination. It also provides a bit that selects the source of the clock as internal or external, a bit to divide the frequency of the signal that will be used as the PROCCLK for the DDR by 2 (this is necessary if that sig−...

  • Page 33: Bifo Disable

    This bit is set to the logic ‘1’ state to connect termination resistors to the Model 6210’s Sync bus. This should be done ONLY on the slave Model 6210 that is at the opposite end of the Sync Bus from the Sync Bus master, or on a stand−alone device that is not connected to the external Sync Bus.

  • Page 34: Master / Slave

    Master / Slave − Bit D0 Set this bit to the logic ‘1’ state to configure a Model 6210 as a Sync bus mas− ter. This bit must also be set to the logic ‘1’ state on any Model 6210 that will not be connected to a Sync Bus.

  • Page 35: Bifo Decimation Register

    Pe nt e k Mo del 6210 Oper ating Manual P age 35 BIFO Decimation Register − R/W @ ‘C6x address 0x0032 0028 The Master Clock, described in Section 3.5, on the previous page, may be further divided to create the Write Enable signal for the VIM motherboard’s mezzanine BIFO. 8 bits are provided for this frequency division, in this register.

  • Page 36: Programmable Gain Amplifier

    When reset, and when powered on, all 3 of these bits default to the logic ‘0’ state. Table 3−6: Model 6210 − Programmable Gain Amplifier Register − R/W @ ‘C6x 0x0032 002C Bit # D 3 1 − D 3...
  • Page 37 P age 37 Programmable Amplifier Gain (continued) 3.7.1 Loading the 12−bit Gain Control Word (continued) Table 3−7: Model 6210 − Gain Control Word vs. Full Scale Input Amplitude Gain Control Word Full Scale Input Amplitude Full Scale Input Amplitude Decimal (Standard)

  • Page 38: Data Format / Signal Path Register

    Model 6210’s Data Format/Signal Path Register, and the subsections that begin below the table describe how the bits are used. Table 3−9: Model 6210 − Data Format / Signal Path Register − R/W @ ‘C6x 0x0032 0030 Bit # D 3 1 − D 4...
  • Page 39 Pack Mode (continued) If the DDR is in the 6210’s data path between the A/D and the VIM mother− board (i.e., if D0 in this register is set to the logic ‘1’ state), then the state of this bit is ignored, and the operating mode of the HSP50214 determines the output...

  • Page 40: Programmable−Gain Amplifier & Low−Pass Filter Bypass

    Pack Mode (continued) When the DDR’s are bypassed, output data by the Model 6210’s A/D con− verters is encoded in true 12−bit 2’s complement format, with the remaining 4 bits of the 16−bit word in which the sample resides indeterminate. The MSB (D15) is used as a sign bit and indicates a negative input voltage when set to the logic ‘1’...

  • Page 41: Ddr Bypass

    DDR Bypass − Bit D0 This bit allows the Model 6210 to function as a simple A/D converter, by routing the output data directly to the BIFO on the VIM motherboard. A/D data will bypass the Intersil HSP50214 DDR chip when this bit is cleared to the logic ‘0’...

  • Page 42: Serial Port 0 Connection Register

    & summarizes the function of its lone bit−field. The connections made by the states of the bits are defined in more detail in the subsections beginning below the table. Table 3−12: Model 6210 − Serial Port 0 Connection Register − R/W @ ‘C6x 0x0032 0038 Bit # D 3 1 −...

  • Page 43: Not Connected

    “Using the Input Gain Adjust Control Signals” in Intersil HSP50214B data sheet, Appendix A of this manual. Table 3−13: Model 6210 − CIC Gain Adjust Register − R/W @ ‘C6x 0x0032 003C Bit # D 3 1 − D 4 Gain Gain Gain...
  • Page 44 32−bit data word is first loaded into four 8−bit master registers internal to the DDR chip from the 8 LSB's of the four DDR Holding Registers on the 6210 (DDR0 − DDR3). The address of the desired destination register in the DDR is then written to the 6210’s DDR Write Destination Address Register (DDR4).
  • Page 45 N o t U s e d N o t A p p l i c a b l e Table 3−16: Model 6210 − DDR Status Read Register − R/W @ ‘C6x 0x0032 003C Bit # D31 − D7...
  • Page 46 Page 4 6 Pe n te k Mo del 6210 Ope rat ing Manual This page is intentionally blank Rev.: C...
  • Page 47 Pe nt e k Mo del 6 2 1 0 O p er a ti n g M a n u a l In t er si l H S P 5 0 2 1 4 B Pa g e A −1 Appendix A: Intersil HSP50214B −...
  • Page 48 Pag e A− 2 In t er si l H S P 5 0 2 1 4 B Pe n te k Mo d el 6 2 1 0 O p e ra t i n g M a n u a l T h is p ag e i s i n te nt io n a ll y b l a nk Rev.: C...

  • Page 49: Ordering Information

    HSP50214B Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts • Up to 65 MSPS Front-End Processing Rates (CLKIN) and [ /Title digitized IF data into filtered baseband data which can be 55MHz Back-End Processing Rates (PROCCLK) (HSP5 Clocks May Be Asynchronous processed by a standard DSP microprocessor.
  • Page 50 HSP50214B Block Diagram ................... . . Pinout .
  • Page 51 HSP50214B PAGE Cartesian to Polar Converter ................. 3-30 .

  • Page 52: Pinout

    HSP50214B Pinout 120 LEAD MQFP TOP VIEW DATARDY IN10 OEBH BOUT15 BOUT14 BOUT13 BOUT12 BOUT11 BOUT10 BOUT9 BOUT8 PROCCLK CLKIN MSYNCI MSYNCO BOUT7 GAINADJ2 BOUT6 GAINADJ1 BOUT5 GAINADJ0 BOUT4 COFSYNC BOUT3 BOUT2 SOFSYNC BOUT1 BOUT0 SYNCIN1 OEBL SYNCIN2...

  • Page 53: Pin Descriptions

    HSP50214B Pin Descriptions NAME TYPE DESCRIPTION Positive Power Supply Voltage. Ground. CLKIN Input Clock. This clock should be a multiple of the input sample rate. All input section processing occurs on the rising edge of CLKIN. The frequency of CLKIN is designated f CLKIN IN(13:0) Input Data.
  • Page 54 HSP50214B Pin Descriptions (Continued) NAME TYPE DESCRIPTION DATARDY Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is available. DA- TARDY is asserted for one PROCCLK cycle during the first clock cycle that data is available on the parallel out bus- ses.
  • Page 55 HSP50214B...

  • Page 56: Functional Description

    HSP50214B Functional Description for frequency division multiple access (FDMA) signals. This high selectivity is achieved with 0.012Hz resolution frequency The HSP50214B Programmable Downconverter (PDC) is an control of the NCO and the sharp filter responses capable agile digital tuner designed to meet the requirements of a with a 255-tap, 22-bit coefficient FIR filter.

  • Page 57: Cdma Based Standards And Applications

    HSP50214B processing the I/Q samples in the DSP µP. The PDC provides and excellent rejection of the portions of the band not being the ability to change the received signal gain and frequency, processed, via the halfband and 255-tap programmable, 22- synchronous with burst timing.

  • Page 58: 14-Bit Input And Processing Resolution

    HSP50214B 14-Bit Input and Processing Resolution the carrier NCO and/or the 5th order CIC filter of all PDCs can be synchronously loaded/updated using SYNCIN1. See The PDC maintains a minimum of 14 bits of processing Control Word 0, Bits 19 and 20 in the Microprocessor Write resolution through to the output, providing over 84dB of Section for details.

  • Page 59: Interpolation Example

    HSP50214B See Figures 4-7 for an interpolated input example, detailing programmed via the microprocessor interface, as shown in the associated spectral results. Figure 9. The bit weighting of the data path through the input threshold detector is shown in Figure 10. The Interpolation Example: threshold is a signed number, so it should be set to the The specifications for the interpolated input example are:...
  • Page 60 HSP50214B 5MHz 10MHz 15MHz 20MHz 25MHz 30MHz 35MHz 40MHz 45MHz 50MHz THE INPUT DATA SPECTRUM SAMPLED AT RATE R = f f’ f’ 3f’ f’ 5f’ 3f’ 7f’ f’ 5MHz 10MHz 15MHz 20MHz 25MHz 30MHz 35MHz 40MHz FIGURE 6. INTERPOLATION SPECTRUM: INTERPOLATE BY 8 THE INPUT DATA WITH ZERO STUFFING; SAMPLE AT RATE R = f’s 4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz 40MHz...

  • Page 61: Figure 9

    HSP50214B ACCUMULATOR ADDR(2:0) INPUT GATING IN(13:0) µPROC LOGIC CLKIN † INPUT_THRESHOLD † INTEGRATION_INTERVAL “0” † START † COUNTER INTEGRATION_MODE CLKIN † CONTINUOUS SINGLE Controlled via microprocessor interface. FIGURE 9. The integration period counter can be set up to run continuously or to count down and stop. Continuous integration counter operation lets the counter run, with sampling occurring every time the counter reaches zero.

  • Page 62: Carrier Synthesizer/Mixer

    HSP50214B Typically, the average input error is read from the Input Level modulo 2 . The output frequency of the NCO is computed Detector port for use in AGC Applications. By setting the threshold to 0, however, the average value of the input signal (EQ.
  • Page 63 HSP50214B The phase of the Carrier NCO can be shifted by adding a synchronization of the phase accumulator starting phase of 10-bit phase offset to the MSB’s (modulo 360 o ) of the output multiple parts. It can also be used to reset the phase of the of the phase accumulator.

  • Page 64: Cic Decimation Filter

    HSP50214B NOTE: COF loading and timing is relative to CLKIN while SOF The decimation factor of the CIC filter is programmed in loading and timing is relative to PROCCLK. Control Word 0, Bits 12 - 7. The CIC Shift Gain is NOTE: T can be 0, and the fastest rate is with 8-bit word width.

  • Page 65: Using The Input Gain Adjust Control Signals

    HSP50214B For 12 bits, Equation 7 becomes: activated by their respective bit location (15-20) in Control Word 7. Any combination of halfband filters may be used, or ]for 5 < R < 40 FLOOR 27 log – (EQ. 8B) all may be bypassed. ≤...
  • Page 66 HSP50214B HALFBAND FILTER INPUT -6dB BANDWIDTH † HALFBAND FILTER 1 HALFBAND FILTER 5 CONTROL WORD 7, BIT 15 HALFBAND FILTER 4 OR f HALFBAND FILTER 3 † HALFBAND FILTER 2 HALFBAND FILTER 2 HALFBAND FILTER 1 -100 CONTROL WORD 7, BIT 16 OR F -120 0.125...

  • Page 67: Examples Of Procclk Rate Calculations

    HSP50214B TABLE 4. HALFBAND FILTER COEFFICIENTS COEFFICIENTS HALFBAND #1 HALFBAND #2 HALFBAND #3 HALFBAND #4 HALFBAND #5 - 0.031303406 0.005929947 -0.00130558 0.000378609 -0.000347137 0.000000000 0.000000000 0.000000000 0.000000000 0.000000000 0.281280518 -0.049036026 0.012379646 -0.003810883 0.00251317 0.499954224 0.000000000 0.000000000 0.000000000 0.000000000 0.281280518 0.29309082 -0.06055069 0.019245148 -0.010158539...

  • Page 68: Programmable Downconverter

    HSP50214B Additionally, the Programmable FIR filter provides for decimation factors, R, from 1 to 16. The processing rate of the Filter Compute Engine is PROCCLK. As a result, the CN-1 frequency of PROCCLK must exceed a minimum value to CN-1 COEFFICIENT COEFFICIENT ensure that a filter calculation is complete before the result is...
  • Page 69 HSP50214B output section. Without gain control, a signal at -72dBFS = 20log ) at the input would have only 4 bits of resolution at the output (12 bits less than the full scale 16 bits). The potential increase in the bit resolution due to processing gain of the filters can be lost without the use of G (dB) the AGC.
  • Page 70 HSP50214B the AGC THRESHOLD value (Control Word 8, Bits 16-28) is TABLE 6A. AGC LIMIT EXPONENT vs GAIN shown in Table 5. Note that the MSB is always zero. The range GAIN(dB) EXPONENT MANTISSA of the AGC THRESHOLD value is 0 to +3.9995. The AGC Error 96.332 Detector output has the identical range.
  • Page 71 HSP50214B TABLE 6C. AGC LIMIT DATA FORMAT CONTROL WORD 9 BIT: FORMAT AGC LOOP FILTER AGC ERROR SCALING µP ERROR (RANGE = -2.18344 TO 2.18344) DETECTOR MSB = 0 SERIAL MANTISSA ∆ MSB = 0 µP LIMIT (11 MANTISSA AGCGNSEL 4 EXPONENT) LOAD †...
  • Page 72 HSP50214B range for the AGC rate is ~ 0.000106 to 3.275dB/output In the HSP50214, a reset event (caused by SYNCIN2 or sample time for a threshold of 1/2 scale. See the notes at the CW25) would clear the AGC loop filter accumulator. In the bottom of Table 9 for calculation of the AGC response times.

  • Page 73: Re-Sampler/Halfband Filter

    HSP50214B The maximum slew rate is ~1.5dB per output sample. See halfband’s rate. The 23-tap filter requires 7 multiplies, and Equation 18. the 15-tap filter requires 5 multiplies to complete a filter calculation. In order to fully evaluate the dynamic range of the PDC, Table 9B is provided, which details the bit weighting from the Using the interpolation halfband filters allows for reduction in input to the AGC Multiplier.
  • Page 74 HSP50214B TABLE 9A. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH AGC LOOP GAIN FILTER OUTPUT ACCUM GAIN ERROR AGC LOOP GAIN AND AGC AGC GAIN ERROR FILTER GAIN MULTIPLIER SHIFT SHIFT SHIFT SHIFT LIMITS BIT RESOLUTION POSITION INPUT WEIGHT (MANTISSA) (OUTPUT) = 15 WEIGHT...
  • Page 75 HSP50214B TABLE 9B. PDC BIT WEIGHTING CIC BIT CIC IN CIC IN WEIGHTS HB DATA MULTI/ WEIGHT INPUT SIN/COS MIX OUT SHIFT = 0 SHIFT = 15 IIIIICCCCC CIC OUT HB DATA IN OUT/FIR IN COEF xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx...

  • Page 76: Timing Nco

    HSP50214B for a baseband CDMA system is 1.2288MHz and PROCCLK is limited to 55MHz. Using the symmetric filter pre-sum approach, PROCCLK limits the programmable FIR to 110MIPS (millions of instructions per second) effective due to symmetry. If the CDMA filter (loaded into the programmable FIR Section) requires an impulse response with a span of 12 chips, the filter at 2x the chip-rate would need 24 taps.
  • Page 77 HSP50214B † EN EXT TIMING NCO SYNC TIMING FILTER PHASE SYNC SYNCIN2 SELECT ACC. † † NCO DIVIDE † (NCO DIVIDE)/2 TIMING PHASE STROBE CARRY OUT = RUN FILTER STROBE TIMING NCO † PHASE OFFSET TE(15:0) CLEAR PROGRAMMABLE PHASE DIVIDER PHASE †...

  • Page 78: Cartesian To Polar Converter

    HSP50214B Cartesian to Polar Converter The magnitude and phase computation requires 17 clocks for full precision. At the end of the 17 clocks, the magnitude The Cartesian to Polar converter computes the magnitude and phase are latched into a register to be held for the next and phase of the I/Q vector.

  • Page 79: Frequency Discriminator

    HSP50214B One caveat to selecting the FIR outputs to be routed directly where D is the discriminator delay defined in Equation 21 to the coordinate converter is that because the I/Q samples (1 < D < 8), f is the Discriminator FIR filter output SAMPOUT for the coordinate conversion are chosen from before the sample rate and CW is the desired center frequency.

  • Page 80: Output Section

    HSP50214B The Discriminator FIR filter input selections are made in request strobes from the controller ensures that data is Control Word 27, Bits 18 and 19. The bit definitions are: transferred only when both the controller and the Programmable Down Converter are ready. The Buffer RAM 00 Item (1) described above.

  • Page 81: Data Ready Signal Assertion Rate

    HSP50214B Data Ready Signal Assertion Rate: Note that the BOUT data word may be at a different rate and skewed in time with respect to DATARDY, depending on the The assertion rate of the DATARDY signal Is the data type of data selected for output. This is because of the timing transition rate of the A output data either [I, |r| or f].

  • Page 82: Serial Direct Output Port Mode

    HSP50214B Serial Direct Output Port Mode identifying the next word is to select a three bit data type identifier which represents the data type to follow the The Serial Direct Output Port Mode offers the ability to source data type. Program these bits into the Control Word construct two serial output data streams, SEROUTA AND 19 field representing the “Link following X data”, where X = SEROUTB, from 16-bit I, Q, magnitude, phase, frequency,...
  • Page 83 HSP50214B † AGC DATA SERIAL OUTPUT TAG BIT † TIMING ERROR DATA SERIAL OUTPUT TAG BIT † FREQUENCY DATA SERIAL OUTPUT TAG BIT † PHASE DATA SERIAL OUTPUT TAG BIT † MAGNITUDE DATA SERIAL OUTPUT TAG BIT † Q DATA SERIAL OUTPUT TAG BIT SOURCE †...

  • Page 84: Serial Output Configuration Example 1

    HSP50214B Serial Output Configuration Example 1: TABLE 15. EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS CONTROL It is desired to output the I data word, followed by the Q data WORD 19 word, followed by the Phase data word on the SEROUTA BIT POSITION FUNCTION VALUE...

  • Page 85: Buffer Ram Output Port

    HSP50214B CONTROL WORD 19, BITS 24-21 = 011 (3 DATA WORDS IN EACH SERIAL OUTPUT) DATA WORD 3 DATA WORD 2 DATA WORD 1 MAGNITUDE SEROUTA DATA WORD 3 DATA WORD 2 DATA WORD 1 SEROUTB MAGNITUDE THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE: NOTE: Once magnitude is identified to follow Q, it must be that way on both serial outputs.

  • Page 86: Fifo Operation Via 16-Bit Μprocessor Interface

    HSP50214B The FIFO mode allows the processor to service the interface only when enough samples are present in the RAM. This mode is provided so that the µProcessor does not have to DUAL PORT φ OUTPUT service the PDC every output sample. An interrupt, φ...
  • Page 87 HSP50214B Figure 38 shows the interface between a 16-bit microprocessor (or other baseband processing engine) and 8 CLKS INTRRP > 4 CLKS the Buffer RAM Output Section of the Programmable Down Converter, configured for data output via the parallel outputs OEAL, AOUT and BOUT.

  • Page 88: Fifo Operation Via 8-Bit Μprocessor Interface

    HSP50214B FIFO Operation via 8-Bit µProcessor READ Interface The Buffer RAM Output may also be accessed via the 8-bit microprocessor interface C(7:0). Figure 41 shows the FIFO conceptual configuration of the 8-bit µprocessor interface. DEPTH Control Word 20, Bit 24 must be set to 0 in order to obtain Buffer RAM data to this output.

  • Page 89: Snap Shot Operation

    HSP50214B R2 R1 R0 A2 A1 A0 SELECTION DUAL 0 RAM I LSB PORT φ 1 RAM I MSB φ LSByte ƒ ƒ 0 RAM Q LSB 1 RAM Q MSB 0 RAM |r| LSB “SET OF WORDS” WRITE 1 RAM |r| MSB ADDRESS SEQUENCER STATUS...

  • Page 90: Avoiding Timing Pitfalls When Using The Buffer Ram Output Port

    HSP50214B The PDC begins to fill the buffer each time an interval Microprocessor Write Section number of samples have passed. The number of sample The Microprocessor Write Section uses an indirect sets the PDC writes into the buffer and is programmed into addressing scheme where a 32-bit data word is first loaded in bits 3-0 of Control Word 21.

  • Page 91: Microprocessor Read Section

    HSP50214B TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE PROCLK STEP A(2:0) C(7:0) COMMENT 0011 1000 Loads 38 into Master Register (7:0) on rising edge of WR. 1101 0000 Loads D0 into Master Register A2-0 READ ADDRESS (15:8) on rising edge of WR. C7-0 OUTPUT DATA C(7:0) 0001 1000 Loads 18 into Master Register...

  • Page 92: Applications

    HSP50214B TABLE 22. DEFINITION OF ADDRESS MAP (Continued) 124 CHANNELS READ STATUS CODE C(2:0) TYPE READ ADDRESS A(2:0) • • • AGC Data AGC (must write to location 10 to sam- and Timing ple) Error 000- AGC LSB (lower 8 bits of linear FREQUENCY Control Word 3 used by multiplier) mmmmmmmm LSB.

  • Page 93: Pdc Configuration

    HSP50214B PDC Configuration References For this example, the PDC is configured as follows: For Intersil documents available on the web, see http://www.intersil.com/ CLKIN: ........39MHz Intersil AnswerFAX (321) 724-7800.
  • Page 94 HSP50214B -110 -110 = CIC INPUT RATE = CIC INPUT RATE -130 -130 FREQUENCY FREQUENCY FIGURE 48A. CIC FILTER RESPONSE FIGURE 48B. HB3 FILTER RESPONSE = CIC INPUT RATE -110 -110 = CIC INPUT RATE -130 -130 FREQUENCY FREQUENCY FIGURE 49A. HB5 FILTER RESPONSE FIGURE 49B.

  • Page 95: Configuration Control Word Definitions

    HSP50214B Configuration Control Word Definitions Note that in the Configuration Control Register Tables, some proper operation of the Microprocessor Write Section. Bits of the available 32 bits in a Control Word are not used. identified as “Reserved” should be programmed to a zero. Unused bits do not need to be written to the Master Register.
  • Page 96 HSP50214B CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN) POSITION FUNCTION DESCRIPTION Reserved Reserved. Integration Mode 0- Integration of magnitude error stops when the interval counter times out. 1- Integration runs continuously. When the interval counter times out, the integrator reloads, and the re- sults of the integration is sent to a register for the processor to read.
  • Page 97 HSP50214B CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK) POSITION FUNCTION DESCRIPTION 31-22 Reserved Reserved. Enable External 0- The SYNCIN2 pin has no effect on the halfband and FIR filters. Filter Sync 1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR, the res- ampler, and the discriminator are reset.
  • Page 98 HSP50214B CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK) POSITION FUNCTION DESCRIPTION 31-28 Reserved Reserved. 27-16 Upper Limit Maximum Gain/Minimum Signal. The upper four bits are used for exponent; the remaining bits form the mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for details. Bit 27 is the MSB.
  • Page 99 HSP50214B CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK) POSITION FUNCTION DESCRIPTION 31-8 Reserved Reserved. Timing NCO Phase These bits are used to offset the phase of the Timing NCO. The range is 0 to 1 times the resampler input period interpreted either as ±...
  • Page 100 HSP50214B CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK) POSITION FUNCTION DESCRIPTION 31-17 Reserved Reserved. 16-15 Phase Multiplier These bits program allow the phase output of the cartesian to polar converter to be multiplied by 1, 2, 4, or 8 (modulo 2π) to remove phase modulation before the frequency is measured.
  • Page 101 HSP50214B CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) (CONTINUED) POSITION FUNCTION DESCRIPTION 17-15 Link Following Q Data The serial data word, or link, following the Q data word is selected using Table 12 (see Output Section). 14-12 Link Following The serial data word, or link, following the MAG data word is selected using Table 12 Magnitude Data (see Output Section).
  • Page 102 HSP50214B CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION (SYNCHRONIZED WITH PROCCLK) (CONTINUED) POSITION FUNCTION DESCRIPTION 11-10 Q Data Serial Output (See I Data Serial Output Tag selection above). Tag Bit Magnitude Data Serial (See I Data Serial Output Tag selection above). Output Tag Bit Phase Data Serial (See I Data Serial Output Tag selection above).
  • Page 103 HSP50214B CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK) POSITION FUNCTION DESCRIPTION Counter and A write to this address initializes the counters and accumulators for testing. Items that are reset are: Accumulator Reset Carrier NCO. 1.
  • Page 104 HSP50214B CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK) POSITION FUNCTION DESCRIPTION (15:12) eeee - AGC Exponent AGC LOAD. Writing to this location generates a strobe to load the AGC loop accumulator with bits (11:5) mmmmmmm - AGC Mantissa (15:5) to the master registers.
  • Page 105 HSP50214B CONTROL WORDS 64-95: DISCRIMINATOR COEFFICIENT REGISTERS (SYNCHRONIZED TO PROCCLK) POSITION FUNCTION DESCRIPTION 31-10 Discriminator FIR The discriminator FIR coefficients are 22-bit-two’s complement. If the filter is symmetric, the coefficients Coefficient are loaded from the center coefficient at address 64 to the last coefficient. If the filter is asymmetric the coefficients C to C are loaded with C...
  • Page 106 HSP50214B Absolute Maximum Ratings Thermal Information θ Supply Voltage ........+7.0V Thermal Resistance (Typical, Note 4) C/W) Input, Output or I/O Voltage .

  • Page 107: Ac Test Load Circuit

    HSP50214B = 5 ±5%, T AC Electrical Specifications to 70 C, Commercial (Note 7); -40 C to 85 C, Industrial (Note 7) (Continued) 65MHz PARAMETER SYMBOL UNITS Hold Time GAINADJ(2:0), IN(13:0), ENI, COF, COFSYNC, and SYNCIN1 from CLKIN Setup Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 to PROCCLK Hold Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 from PROCCLK...

  • Page 108: Waveforms

    HSP50214B Waveforms A(2-0) C(0-7) C(0-7), A(0-2) FIGURE 50. TIMING RELATIVE TO WR FIGURE 51. TIMING RELATIVE TO RD CLKIN IN(13:0), COF GAINADJ(2:0), ENI, COFSYNC, SYNCIN1 2.0V 0.8V FIGURE 52. OUTPUT RISE AND FALL TIMES FIGURE 53. TIMING RELATIVE TO CLKIN PROCCLK AGCGNSEL, MCSYNC1...
  • Page 109 Pe nt e k Mo del 6 2 1 0 O p er a ti n g M a n u a l An a l o g D e v i ces AD 6 6 4 0 P ag e B −1 Appendix B: Analog Devices AD6640 −...
  • Page 110 Pag e B −2 A n a l o g D e v i ces AD 6 6 4 0 Pe n te k Mo d el 6 2 1 0 O p e ra t i n g M a n u a l T h is p ag e i s i n te nt io n a ll y b l a nk Rev.: C...
  • Page 111 12-Bit, 65 MSPS IF Sampling A/D Converter AD6640 FEATURES FUNCTIONAL BLOCK DIAGRAM 65 MSPS Minimum Sample Rate 80 dB Spurious-Free Dynamic Range IF-Sampling to 70 MHz 710 mW Power Dissipation Single +5 V Supply On-Chip T/H and Reference +2.4V Twos Complement Output Format AD6640 REFERENCE 3.3 V or 5 V CMOS-Compatible Output Levels...
  • Page 112 AD6640–SPECIFICATIONS DC SPECIFICATIONS = +5 V, DV = +3.3 V; T = –40 C, T = +85 C) Test AD6640AST Parameter Temp Level Units RESOLUTION Bits ACCURACY No Missing Codes +25°C GUARANTEED Offset Error Full –10 Gain Error Full –10 % FS ±...
  • Page 113 AD6640 SWITCHING SPECIFICATIONS = +5 V, DV = +3.3 V; ENCODE & ENCODE = 65 MSPS; T = –40 C, T = +85 C) Test AD6640AST Parameter (Conditions) Temp Level Units Maximum Conversion Rate Full MSPS Minimum Conversion Rate Full MSPS Aperture Delay (t +25°C...
  • Page 114 AD6640 ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Test Level Parameter Units – 100% production tested. ELECTRICAL – 100% production tested at +25°C, and sample tested at Voltage specified temperatures. AC testing done on sample Voltage basis. Analog Input Voltage III –...
  • Page 115 AD6640 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 2, 36, 37, 40, 41 +3.3 V/+5 V Power Supply (Digital). Powers output stage only. ENCODE Encode Input. Data conversion initiated on rising edge. ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to Ground for single-ended clock mode.
  • Page 116 AD6640 DEFINITION OF SPECIFICATIONS Power Supply Rejection Ratio Analog Bandwidth (Small Signal) The ratio of a change in input offset voltage to a change in The analog input frequency at which the spectral power of the power supply voltage. fundamental frequency (as determined by the FFT analysis) is Signal-to-Noise-and-Distortion (SINAD) reduced by 3 dB.
  • Page 117 Equivalent Circuits–AD6640 ANALOG INPUTS N + 1 ENCODE INPUTS (ENCODE) DIGITAL OUTPUTS N – 2 N – 1 (D11–D0) Figure 1. Timing Diagram CURRENT MIRROR D0–D11 Figure 2. Analog Input Stage CURRENT MIRROR Figure 5. Digital Output Stage ENCODE ENCODE TIMING CIRCUITS 2.4V...
  • Page 118 AD6640 –Typical Performance Characteristics ENCODE = 65MSPS ENCODE = 65MSPS AIN = 2.2MHz TEMP = –40 C, +25 C, & +85 C T = +25 C T = –40 C, +85 C 13.0 19.5 26.0 32.5 ANALOG INPUT FREQUENCY – MHz FREQUENCY –...
  • Page 119 AD6640 AIN = 19.5MHz ENCODE = 65MSPS AIN = 15.0, 16.0MHz NO DITHER WORST SPUR 13.0 19.5 26.0 32.5 SAMPLE RATE – MSPS FREQUENCY – MHz Figure 16. SNR, Worst Spurious vs. Encode Figure 13. Two Tones at 15.0 MHz & 16.0 MHz ENCODE = 65MSPS dBFS AIN = 2.2MHz...
  • Page 120 AD6640 ENCODE = 65MSPS ENCODE = 65MSPS AIN = 19.5MHz @ –36dBFS AIN = 19.5MHz @ –36dBFS –20 –20 NO DITHER DITHER = –32.5dBm –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 13.0 19.5 26.0 32.5 13.0 19.5 26.0 32.5 FREQUENCY –...
  • Page 121 AD6640 THEORY OF OPERATION The AD6640 analog-to-digital converter (ADC) employs a two- ENCODE ENCODE SOURCE stage subrange architecture. This design approach ensures ENCODE 12-bit accuracy, without the need for laser trim, at low power. 0.01 F As shown in the functional block diagram, the AD6640 has AD6640 complementary analog input pins, AIN and AIN.
  • Page 122 AD6640 To take full advantage of this high input impedance, a 20:1 T1–1T SINE transformer would be required. This is a large ratio and could ENCODE SOURCE result in unsatisfactory performance. In this case, a lower AD6640 step-up ratio could be used. For example, if R were set to ENCODE 260 ohms, along with a 4:1 transformer, the input would match...
  • Page 123 AD6640 the device. A full-scale transition can cause up to 120 mA the sides should be implemented. The addition of small value (12 bits × 10 mA/bit) of current to flow through the digital resistors between the AD9631 and the AD6640 will prevent output stages.
  • Page 124 AD6640 The analog input range of the PCB is ± 0.5 volts (i.e., signal ac- AD6640 output data is latched using 74LCX574 (U3, U4) coupled to AD6640). latches following 348 ohm series resistors. The resistors limit the current that would otherwise flow due to the digital output The encode signal may be generated using an onboard crystal slew rate.
  • Page 125 AD6640 +5VA 74LCX574 74LVQ00 (+5VA) BUFLAT 0.1 F ENCODE (+3.3V OR +5.0V) INPUT 39 38 36 35 T4–1T TWO COMPLEMENT ENCODE BUFFERED OUTPUTS ENCODE ANALOG BUFLAT T4–1T INPUT AD6640 (LSB) D0 74LCX574 0.01 F 0.1 F 0.01 F 0.1 F 12 13 14 15 16 17 18 19 20 21 22 +5VA...
  • Page 126 AD6640 Figure 37. AD6640ST/PCB Top Side Silkscreen Figure 39. AD6640ST/PCB Top Side Copper Figure 38. AD6640ST/PCB Bottom Side Silkscreen Figure 40. AD6640ST/PCB Bottom Side Copper (Positive) NOTE: Evaluation boards are often updated, consult factory for latest version. REV. 0 –16–...
  • Page 127 AD6640 Figure 41. AD6640ST/PCB Ground Layer (Negative) Figure 42. AD6640ST/PCB “Split” Power Layer (Negative) REV. 0 –17–...
  • Page 128 AD6640 is used for demodulation, different routines may be used to DIGITAL WIDEBAND RECEIVERS demodulate different standards such as AM, FM, GMSK or any Introduction other desired standard. In addition, as new standards arise or Several key technologies are now being introduced that may new software revisions are generated, they may be field installed forever alter the vision of radio.
  • Page 129 AD6640 AD6620 +5V (A) +3.3V (D) CMOS ADSP-2181 (REF. FIG 45) PRESELECT 5–15MHz BUFFER FILTER PASSBAND I & Q NETWORK DATA DRIVE CONTROLLER AD6640 1900MHz INTERFACE ENCODE M/N PLL SYNTHESIZER ENCODE 65.00MHz REFERENCE CLOCK Figure 46. Simplified Wideband PCS Receiver System Requirements power dissipation is not a function of sample rate.
  • Page 130 AD6640 faster the signal is digitized, the wider the distribution of noise. Overcoming Static Nonlinearities with Dither Since the integrated noise must remain constant, the actual Typically, high resolution data converters use multistage noise floor is lowered by 3 dB each time the sample rate is techniques to achieve high bit resolution without large com- doubled.
  • Page 131 AD6640 The simplest method for generating dither is through the use of The first noise calculation to make is based on the signal band- a noise diode (Figure 48). In this circuit, the noise diode NC202 width at the antenna. In a typical broadband cellular receiver, generates the reference noise that is gained up and driven by the the IF bandwidth is 12.5 MHz.
  • Page 132 AD6640 Figures 21 and 24 in Typical Performance Characteristics illus- IF Sampling, Using the AD6640 as a Mix-Down Stage trate a multicarrier, IF Sampling System. By using dither, all Since performance of the AD6640 extends beyond the baseband spurious components are forced below 90 dBFS (Figure 24). region into the third Nyquist zone, the converter has many uses The dashed line illustrates how a 5 MHz bandpass filter could as a mix-down converter in both narrowband and wideband...
  • Page 133 AD6640 SYNC 1 AD6620 (1) EIGHT WIDEBAND FRONT ENDS AD6620 (2) ANTENNA 1 AD6620 (3) AD6640 AD6620 (30) COMMON LO AD6620 (31) AD6620 (32) ANTENNA 2 AD6640 AD6620s (32 CHANNELS) COMBINE SIGNALS FROM EIGHT ANTENNA'S SYNC 1 AD6620 (1) ADSP-21xx AD6620 (2) ANTENNA 3 AD6620 (3)
  • Page 134 AD6640 AD6640AST OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 44-Terminal Plastic Thin Quad Flatpack (ST-44) 0.063 (1.60) 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45) SEATING PLANE 0.394 TOP VIEW (10.0) (PINS DOWN) 0.006 (0.15) 0.002 (0.05) 0.018 (0.45) 0.031 (0.80) 0.057 (1.45) 0.012 (0.30) 0.053 (1.35)
  • Page 135 Pe nt e k Mo del 6 2 1 0 O p er a ti n g M a n u a l An a l o g D e v i ces AD 6 0 3 Pag e C −1 Appendix C: Analog Devices AD603 −...
  • Page 136 Pag e C −2 A n a l o g D e v i ces AD 6 0 3 Pe n te k Mo d el 6 2 1 0 O p e ra t i n g M a n u a l T h is p ag e i s i n te nt io n a ll y b l a nk Rev.: C...
  • Page 137 Low Noise, 90 MHz Variable-Gain Amplifier AD603* 1 V to span the central 40 dB of the gain range. An over- and FEATURES “Linear in dB” Gain Control underrange of 1 dB is provided whatever the selected range. The gain-control response time is less than 1 µs for a 40 dB change. Pin Programmable Gain Ranges –11 dB to +31 dB with 90 MHz Bandwidth The differential gain-control interface allows the use of either...
  • Page 138 = 5 V, –500 mV ≤ V ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB Gain (@ T = 25 C, V AD603–SPECIFICATIONS Range, R = 500 , and C = 5 pF, unless otherwise noted.) Model AD603 Parameter...
  • Page 139 AD603 ABSOLUTE MAXIMUM RATINGS PIN FUNCTION DESCRIPTIONS Supply Voltage ± V ......± 7.5 V Internal Voltage VINP (Pin 3) .
  • Page 140 AD603 technique is employed to interpolate between these tap-points, THEORY OF OPERATION indicated by the “slider” in Figure 1, thus providing continuous The AD603 comprises a fixed-gain amplifier, preceded by a attenuation from 0 dB to 42.14 dB. It will help, in understanding broadband passive attenuator of 0 dB to 42.14 dB, having a the AD603, to think in terms of a mechanical means for moving gain-control scaling factor of 40 dB per volt.
  • Page 141 AD603 The Gain-Control Interface GPOS VPOS VPOS The attenuation is controlled through a differential, high- AD603 impedance (50 MΩ) input, with a scaling factor which is GNEG laser-trimmed to 40 dB per volt, that is, 25 mV/dB. An internal bandgap reference ensures stability of the scaling with respect to VINP VNEG VNEG...
  • Page 142 AD603 Optionally, when a resistor is placed from FDBK to COMM, There are several ways of connecting the gain-control inputs in higher gains can be achieved. This fourth mode is of limited cascaded operation. The choice depends on whether it is impor- value because of the low bandwidth and the elevated output off- tant to achieve the highest possible Instantaneous Signal-to-Noise sets;...
  • Page 143 AD603 –40.00dB –51.07dB –42.14dB –8.93dB –42.14dB INPUT 31.07dB 31.07dB OUTPUT GPOS GNEG GPOS GNEG –20dB = 0.473V = 1.526V = 0V –11.07dB –42.14dB 31.07dB INPUT 31.07dB 31.07dB OUTPUT GPOS GNEG GPOS GNEG 20dB = 0.473V = 1.526V = 1.0V –28.93dB –2.14dB INPUT 31.07dB...
  • Page 144 AD603 –0.5 –1.0 –1.5 –2.0 –0.2 –0.2 0.0 0.2 0.4 0.6 1.2 1.4 1.6 1.8 2.0 2.2 Figure 9. SNR for Cascaded Stages—Sequential Control Figure 11. Gain Error for Cascaded Stages–Parallel Control –0.5 –1.0 –1.5 –2.0 –0.2 –0.2 0.0 0.2 0.4 0.6 1.2 1.4 1.6 1.8...
  • Page 145 AD603 THEORY OF THE AD603 A Low Noise AGC Amplifier Figure 15 shows the ease with which the AD603 can be connected as an AGC amplifier. The circuit illustrates many of the points previously discussed: It uses few parts, has linear-in-dB gain, operates from a single supply, uses two cascaded amplifiers in sequential gain mode for maximum S/N ratio, and an external resistor programs each amplifier’s gain.
  • Page 146 AD603 output signal. The automatic gain control voltage, V , is the This resistor also serves to lower the peak current in Q1 when time-integral of this error current. In order for V (and thus more typical signals (usually, sinusoidal) are involved, and the the gain) to remain insensitive to short-term amplitude fluctuations 1.8 kHz LP filter it forms with C helps to minimize distortion...
  • Page 147 AD603 REF LEVEL /DIV MARKER 505 156.739Hz REF LEVEL /DIV MARKER 505 156.739Hz –11.850dB 1.000dB MAG (UDF) –15.859dB 8.100dB 1.000dB MAG (UDF) 4.127dB 0.0deg 45.000deg MARKER 505 156.739Hz 0.0deg 45.000deg MARKER 505 156.739Hz PHASE (UDF) –1.378deg PHASE (UDF) –1.338deg 2.50 45MHz 2.00 1.50...
  • Page 148 AD603 100k 100M 100k 100M 100k 100M FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz Figure 25. Input Impedance vs. Figure 26. Input Impedance vs. Figure 27. Input Impedance vs. Frequency (Gain = –10 dB) Frequency (Gain = +10 dB) Frequency (Gain = +30 dB) 4.5V INPUT GND...
  • Page 149 AD603 = 25 C 30MHz 10MHz = 25 C = 50 = 50 TEST SETUP TEST SETUP 0.1 F 70MHz FIGURE 34 FIGURE 34 HP3326A DUAL 20MHz CHANNEL HP3585A SYNTHESIZER AD603 SPECTRUM 50MHz ANALYZER 0.1 F 10MHz –5V DATEL DVC 8500 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GAIN –...
  • Page 150 AD603 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Cerdip (Q-8) 0.055 (1.4) 0.005 (0.13) 0.310 (7.87) 0.220 (5.59) PIN 1 0.320 (8.13) 0.405 (10.29) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) 0.150 (3.81) 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) SEATING 0.023 (0.58)
  • Page 151 Pe nt e k Mo del 6210 Oper ating Manual L in e ar T e c hn ol o gy L T C 1 45 1 P a g e D − 1 Appendix D: Linear Technology LTC1451 − 12−bit Rail to Rail DAC Included for your reference on the following pages is the data sheet for the LTC1451 12−...
  • Page 152 Pag e D − 2 Pe nte k Mo del 6210 Ope ra ting Ma nu al L in ea r T e c h n o l o g y L T C 1 45 1 T h is p ag e i s i n te nt io n a ll y b l a nk...
  • Page 153 LTC1451 LTC1452/LTC1453 12-Bit Rail-to-Rail Micropower DACs in SO-8 FEATURES DESCRIPTIO ® 12-Bit Resolution The LTC 1451/LTC1452/LTC1453 are complete single Buffered True Rail-to-Rail Voltage Output supply, rail-to-rail voltage output 12-bit digital-to-analog 3V Operation (LTC1453), I : 250µA Typ converters (DACs) in an SO-8 package. They include an 5V Operation (LTC1451), I : 400µA Typ output buffer amplifier and an easy-to-use 3-wire...

  • Page 154: Electrical Characteristics

    LTC1451 LTC1452/LTC1453 ABSOLUTE AXI U RATI GS (Note 1) Operating Temperature Range to GND ..........– 0.5V to 7.5V Commercial ........... 0°C to 70°C TTL Input Voltage ........– 0.5V to 7.5V Industrial ......... – 40°C to 85°C ........– 0.5V to V + 0.5V Storage Temperature Range ....
  • Page 155 LTC1451 LTC1452/LTC1453 ELECTRICAL CHARACTERISTICS denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 4.5V to 5.5V (LTC1451), 2.7V to 5.5V (LTC1452/LTC1453), ≤ V internal or external reference (V /2), V and REF unloaded, unless otherwise noted.
  • Page 156 LTC1451 LTC1452/LTC1453 ELECTRICAL CHARACTERISTICS denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 5V (LTC1451LTC1452), V = 3V (LTC1453). LTC1451/LTC1452 LTC1453 SYMBOL PARAMETER CONDITIONS UNITS Digital I/O Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage = –...
  • Page 157 LTC1451 LTC1452/LTC1453 TYPICAL PERFOR A CE CHARACTERISTICS LTC1451 LTC1451 Supply Current vs Logic Input LTC1451 Pull-Down Voltage vs Output Sink Voltage Output Swing vs Load Resistance Current Capability 1.15 1000 ALL DIGITAL INPUTS 1.05 TIED TOGETHER FULL SCALE TIED TO GND 125°C 0.95 0.85...
  • Page 158 LTC1451 LTC1452/LTC1453 PI FU CTIO S CLK: The TTL Level Input for the Serial Interface Clock. GND: Ground. : The TTL Level Input for the Serial Interface Data. Data REF: The Output of the Internal Reference and the Input on the D pin is latched into the shift register on the rising to the DAC Resistor Ladder.
  • Page 159 LTC1451 LTC1452/LTC1453 DEFI ITIO S Resolution (n): Resolution is defined as the number of Integral Nonlinearity (INL): End-point INL is the maxi- digital input bits, n. It defines the number of DAC output mum deviation from a straight line passing through the states (2 ) that divide the full-scale range.
  • Page 160 LTC1451 LTC1452/LTC1453 OPERATIO Reference Serial Interface The data on the D input is loaded into the shift register The LTC1451 includes an internal 2.048V reference, mak- ing 1LSB equal to 1mV (gain of 2). The LTC1453 has an on the rising edge of the clock. The MSB is loaded first. The internal reference of 1.22V with a full scale of 2.5V (gain of DAC register loads the data from the shift register when CS/LD is pulled high.
  • Page 161 LTC1451 LTC1452/LTC1453 TYPICAL APPLICATIO S An Isolated 4mA to 20mA Process Controller Has 3.3V Minimum Loop Voltage LOOP 3.3V TO 30V ® 1121-3.3 1µF FROM OPTO- LTC1453 ISOLATED LT1077 INPUTS CS/LD 2N3440 – 10Ω 11451/2/3 TA04 3.3V OPTO-ISOLATORS CS/LD 500Ω 4N28 CS/LD This circuit shows how to use an LTC1453 to make an...
  • Page 162 LTC1451 LTC1452/LTC1453 TYPICAL APPLICATIO S 12-Bit 3V to 5V Voltage Output DAC LTC1451: 4.5V TO 5.5V LTC1452: 2.7V TO 5.5V LTC1453: 2.7V TO 5.5V 0.1µF µP LTC145X OUTPUT CS/LD LTC1451: 0V TO 4.095V LTC1452: 0V TO 2 • REF LTC1453: 0V TO 2.5V TO NEXT DAC FOR 1451/2/3 TA03 LTC1451: 2.048V...
  • Page 163 LTC1451 LTC1452/LTC1453 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 0.300 – 0.325 0.045 – 0.065 (3.302 ± 0.127) (1.143 –...
  • Page 164 LTC1451 LTC1452/LTC1453 TYPICAL APPLICATION This circuit shows how to make a bipolar output 12-bit the onboard reference is always sourcing current and DAC with a wide output swing using an LTC1451 and an never has to sink any current even when V is at full- LT1077.

  • Page 165: E.1 Introduction

    0 = Not Selected reading Clock line EEPROM Format Example Shown on the next page is the contents of an EEPROM, the example shows the Pentek Model 6210, and an explanation of what each word is used for. Rev.: C...

  • Page 166: Table E−2: Eeprom Example (Model 6210 Shown)

    Page E −2 Pe nte k Mo d el 6210 Op e ra ting Ma nu al EEPROM Format Example (continued) Table E−2: EEPROM Example (Model 6210 shown) Global SRAM EEPROM Word Contents Comments Locations Location 0x0000 z900 00/01 Valid data flag 0x00EE C0DE Model, Model Extension −...

  • Page 167: F.1 Introduction

    65 MHz crystal, PROCCLK must be divided by 2 (this is the default setting − set by bit D4 in the 6210’s Control Register). In order to achieve the maximum chip sampling rate and bandwidth, a 55 MHz clock is required; on the standard Model 6210 (or Option 020), PROCCLK must be divided by 2 for inputs higher than 55 MHz.

  • Page 168: F.3 Calculating The Low Pass Bandwidth

    Pag e F −2 Pe n te k Mo d el 6 2 1 0 O p e ra t i n g M a n u a l Calculating the Low Pass Bandwidth The specifications listed above use one halfband filter section. The throughput is set by the selected filters and the PROCCLK rate.

  • Page 169: F.6 Additional Information/References

    Pe nt e k Mo del 62 10 O p er a ti ng M a n u a l P a g e F −3 Additional Information/References Intersil’s Data Sheet #4450.2 “HSP50214B Programmable Downconverter”, 2/99 is included as Appendix A of this manual.
  • Page 170 Pag e F −4 Pe n te k Mo d el 6 2 1 0 O p e ra t i n g M a n u a l T h is p ag e i s i n te nt io n a ll y b l a nk Rev.: C...

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