Pentek 6210 Operating Manual page 101

CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) (CONTINUED)
BIT
POSITION FUNCTION
17-15 Link Following Q Data The serial data word, or link, following the Q data word is selected using Table 12
14-12 Link Following
Magnitude Data
11-9 Link Following Phase
Data
8-6 Link Following
Frequency Data
5-3 Link Following AGC
Level Data
2-0 Link Following Timing
Error Data
CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION
BIT
POSITION FUNCTION
31-26 Reserved
25 Data Source for Least
Significant Bytes of
AOUT and BOUT
24 Buffered Output Mode
Interface
23-22 AOUT Direct Parallel
Output Mode Data
Source
21-20 BOUT Direct Parallel
Output Mode Data
Source
19 Serial Output Sync Po-
larity
18 Serial Output Clock
Polarity
17 Serial Output Sync Po-
sition
16-14 Serial Out Clock
Divider
13-12 I Data Serial Output
Tag Bit
3-53
HSP50214B
(see Output Section).
The serial data word, or link, following the MAG data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the PHAS data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the FREQ data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the AGC data word is selected using Table 12
(see Output Section).
The serial data word, or link, following the TIMER data word is selected using Table 12
(see Output Section).
(SYNCHRONIZED WITH PROCCLK)
Reserved.
Output LSBytes, bits (7:0), of AOUT and BOUT can provide:
0- Buffer RAM Mode Output or,
1- Parallel Direct Mode Output.
Buffered Mode Output interfaces to either:
0- 8-bit µP (address = µP ASEL(5:#); CLK = µP RAM read).
1- 16-bit µP (address = SEL(2:0); CLK = OEBL).
The data word sent by the Direct Parallel Output Mode to AOUT is:
00- I Data. (2's complement)
01- Magnitude. (O; unsigned binary)
1X- Frequency. (2's complement)
The data word sent by the Direct Parallel Output Mode to BOUT is:
00- Q Data (2's complement).
01- Phase (2's complement).
1X- Magnitude (O; unsigned binary).
0- Normal Sync Mode (active high).
1- Sync Inverted (active low).
0- Output Clock Inverted rising edge aligns with data transitions.
1- Output Clock Normal falling edge aligns with data transitions.
0
0- Sync is asserted one bit time after the last bit of the serial word (Late Mode).
1- Sync is asserted one bit time prior to the first bit of the serial word (Early Mode).
000- Serial Output at PROCCLK/16.
001- Serial Output at PROCCLK/8.
010- Serial Output at PROCCLK/4.
011- Serial Output at PROCCLK/2.
1XX- Serial Output at PROCCLK rate.
00- No Tag Bit. LSB of word is passed.
01- 0 Tag Bit. LSB of word is set to zero.
1X- 1 Tag Bit. LSB of word is set to one.
DESCRIPTION
DESCRIPTION
1