Pentek 6210 Operating Manual page 20

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2.4 Sync Bus − Serial I/O Connector
2.4.1
MCLK
MSYNC
SYNC1
SYNC2
PRCLK
Master / Slave
(Control Reg., D0)
EXT CLK
Input
(Control Reg., D2)
Figure 2−5: Model 6210 − Block Diagram of Clock and Sync Signal Sources
DDR 1 is controlled by VIM Motherboard Processor A or C, and DDR2 is controlled by
Note
Processor B or D, depending where the VIM module is installed on the motherboard.
Rev.: C
Signals for Synchronizing Multiple Boards
LVDS
Receiver
LVDS
Driver
Master Clock
Divide
Divider Register
˛
by N
Clock Select
64 MHz
Oscillator
Pe n te k Mo del 6210 Ope rat ing Manual
(continued)
(DIV0)
Divide
by 2
PRCLK Freq.
(Control Reg., D4)
(continued)
AD6640
A/D 1
CLK IN
CLK IN PRCLK
MSYNC In MSYNC Out
SYNC1
SYNC Out
SYNC2
DDR 2
HSP 50214B
AD6640
A/D 2
CLK IN
CLK IN PRCLK
MSYNC In MSYNC Out
SYNC1
SYNC Out
SYNC2
DDR 1
HSP 50214B