Read/Clear Status Register 0 - EKF SC2-PRESTO CompactPCI User Manual

User Guide • SC2-PRESTO • CompactPCI
Bit
4:3 WDGT0:WDGT1
Maximum Watchdog retrigger time:
0:0 2 sec
1:0 10 sec
0:1 50 sec
1:1 250 sec
2 WDGTRG
Retrigger Watchdog. Any change of this bit will retrigger the watchdog.
After a system reset the watchdog is in an inactive state. The watchdog is armed on the 1
1 PGLED
0=Red part of the front panel LED PG is off (Default)
1=Red part of the front panel LED PG is blinking
0 SRES
0=Normal operation (Default)
1=A full system reset is performed

Read/Clear Status Register 0

Write: SMBus Address 0xB0
Read: SMBus Address 0xB1
Bit
7 PF18S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.8S voltage regulator
6 PF15S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.5S voltage regulator
5 PF135S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.35S voltage regulator
4 RESERVED
Always read as 0
3 PF105M
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.05M voltage regulator
2 PF105S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.05S voltage regulator
1 RESERVED
Always read as 0
0 PFVRC
0=Normal operation
1=Last system reset may be caused by a power failure of the CPU voltage regulator
The bits in this register are sticky, i.e. their state will be kept even if a system reset occurs. To clear the
bits a write to the register with arbitrary data may be performed.
© EKF
®
Serial CPU Board • Intel® Core
Description CMD_CTRL0
Description CMD_STAT0
-53-
TM
4xxx Processor
st
edge of this bit.
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