Quarter-Inch Tape Controller - Sun Microsystems Sun Workstation 100U System Manager's Manual

Hardware Configuration and Expansion
Sun 100/150 Installation Manual
There are also board placement considerations involved in installation:
• The TAPEMASTER board should not be placed on the same P2 connector as the Sun-2
CPU and Memory Boards.
• The nine-track tape controller is a Multibus master. This means that the relative number
of its slot determines its priority (slot 1 is the highest-priority master). The board must be
placed in a lower-priority position than the CPU. If you have a Xylogics 450 SMD Con-
troller Board in your system as well, place the T APEMASTER Board in a higher-priority
position; otherwise, the Xylogics board will lock out the T APEMASTER (due to its higher
data transfer rate).
To cable up the tape controller, connect the 50-pin ribbon cable coming from the backpanel
connector labelled "DISK/TAPE COMMAND B" to the "J2" connector in the center of the
T APEMASTER board. The 50-pin ribbon cable from the back panel connector labelled
"TAPE COMMAND A" should go to the "Jl" edge connector of the TAPEMASTER board.
As shipped, the tape controller board should already be set up to work correctly in a Sun sys-
tem. Refer to the Computer Products Corporation TAPEMASTER Manual for details of
configuring the board if required.
8.9. Quarter-Inch Tape Controller
The Sun tape interface board consists of an interface to an Archive 1/4" streaming tape unit
and 256 KBytes of Multibus memory with parity. The tape controller is not a bus master, and
boards which are Rev. C or 'greater' may actually be placed in a slot between bus masters (in
the ModeI100U), as they pass bus priority through.
Note that you must disable the Multibus memory on the Tape Controller Board if you have a
Sun-2 CPU in your system. To do this, open all switches on switch package U50, as described
below.
There are four
~position
DIP switches on the tape controller board. They are used to select the
interrupt level at which the tape controller will interrupt the processor, select the base address
for the Multibus memory on the board, and to select the base address for the Multibus I/O
registers which communicate commands and status information between the tape controller and
the central processor.
With the Multibus connectors facing you, the switches are all in the lower left hand corner of
the board, at component locations U52, U50, US3, and US6. US2 is in the lower left-hand
corner of the board; USO is directly above U52; US3 is to the immediate right of U50; and US6 is
to the immediate right of U53. For each package, switch #1 is on the right and switch #8 is
on the left.
Switch package US2 selects the interrupt level; switch #1 selects interrupt level 0, switch #8
selects interrupt level 7. The desired switch should be dosed (or ON); all others should be left
open (or OFF). The table below shows the switch settings. The Sun system is configured to
run with level 3 interrupts from the quarter-inch tape controller.
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Revision H of 12 March 1984