Table of Contents
Advertisement
www.ti.com
2.3
Signal Descriptions
The DDR2 memory controller signals are shown in
features are included:
The maximum data bus is 32-bits wide.
The address bus is 13-bits wide with an additional 3 bank address pins.
Two differential output clocks driven by internal clock sources.
Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.
One chip select signal and one clock enable signal.
Pin
Type
DDR_CLK,
O/Z
DDR_CLK
DDR_CKE
O/Z
DDR_CS
O/Z
DDR_WE
O/Z
DDR_RAS
O/Z
DDR_CAS
O/Z
DDR_DQM[3:0]
O/Z
DDR_DQS[3:0]
I/O/Z
DDR_BA[2:0]
O/Z
DDR_A[12:0]
O/Z
DDR_D[31:0]
I/O/Z
DDR_ZN,
O
DDR_ZP
SPRUEM4A – November 2007
Submit Documentation Feedback
Figure 3. DDR2 Memory Controller Signals
DDR2
memory
DDR_DQM[3:0]
controller
DDR_DQS[3:0]
DDR_BA[2:0]
DDR_A[12:0]
DDR_D[31:0]
Table 2. DDR2 Memory Controller Signal Descriptions
Description
Clock: Differential clock outputs.
Clock enable: Active high.
Chip select: Active low.
Write enable strobe: Active low, command output.
Row address strobe: Active low, command output.
Column address strobe: Active low, command output.
Data mask: Output mask signal for write data.
Data strobe: Active high, bi-directional signals. Output with write data, input with read data.
Bank address: Output, defining which bank a given command is applied.
Address: Address bus.
Data: Bi-directional data bus. Input for read data, output for write data.
Output impedance control: Required to set the DDR2 output impedance. Connected by way of
a 200-ohm resistor to power and ground (see
4 times the desired impedance of the output buffer. By changing the size of the resistor, the
DDR2 outputs can be tuned to match the board load, if necessary.
Figure 3
and described in
DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_WE
DDR_RAS
DDR_CAS
200
DDR_ZN
200
DDR_ZP
Figure
3). The resistor should be chosen to be
Peripheral Architecture
Table
2. The following
DDR2 Memory Controller
11
Advertisement
Table of Contents
