Table of Contents
Advertisement
Lattice Semiconductor
source for various Lattice FPGA evaluation boards. The contents of this user's guide include demo operation,
top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board con-
nectors, switches and a complete set of schematics.
• QuickSTART Guide – Provides information on connecting the evaluation board, running the pre-loaded evalua-
tion demo.
The contents of this user's guide include demo operation, programming instructions, top-level functional descrip-
tions of the evaluation board, descriptions of the on-board connectors, switches and a complete set of schematics
of the board. For a complete list of the various connections and interfaces used on the ispClock5400D Evaluation
Board, please refer to the schematics in Appendix A.
The ispClock5400D Evaluation Board is 100% lead free and RoHS compliant as Lattice Semiconductor Corpora-
tion is sensitive to environmental issues.
Additional resources relating to the ispClock5400D Evaluation Board are available on the Lattice web site. Go to:
www.latticesemi/.com/boards
as well as sample programs and links to other related items.
Figure 1. ispClock5400D Evaluation Board
Software Requirements
Install the following software before you begin developing designs for the ispClock5400D Evaluation Board:
®
• PAC-Designer
5.2 (ispClock5406D support)
®
• Optional: ispLEVER
/Pro (LatticeECP3 support)
• Optional: ispVM™ System 17.5
and navigate to the appropriate link. Updates to this document can be found there,
ispClock5400D Evaluation Board
3
User's Guide
Advertisement
Table of Contents
