Lattice Semiconductor ispClock5400D User Manual page 13

Lattice Semiconductor
Figure 13. Scope Plot - 156.25 MHz Output
The 156.25 MHz clock from the REFB input output appears on the scope.
6. Toggle position 3 of the DIP switch (USER3) on the evaluation board back to the 1=REF-SEL position to
enable the 100 MHz input reference clock, REFA_P/N input.
In-System Changes via I
This section demonstrates the I
ture allows you to override many device parameters of the device programming and make in-system changes to
almost all phase, time, reference and frequency settings of the ispClock5406D. The feature allows dynamic
time/phase skew for testing and margining of the output clocks, on every bank output pair. Upon device reset the
device returns to the configuration stored in E
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The PAC-Designer I C Design Utility for the ispClock5406D provides a software interface to the ispClock5406D I
registers such as output group and PLL controls.
The demo will apply all the changes you performed by reprogramming the device in the earlier procedures of the
user's guide.
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To set up the I C ispDOWNLOAD Cable interface:
1. If you have not done so already, connect the ispDOWNLOAD cable to the I
Figure 41).
2. Start PAC-Designer.
3. Choose File > Open...
The Open dialog appears. (Note for PAC-Designer 5.2: See the Troubleshooting section of this user's guide for
information on a correction required prior to using the I
4. Browse the Base_Demo_CLK5406.PAC project and choose Open.
The ispPAC-CLK5406D schematic view appears.
5. From PAC-Designer choose Tools > Design Utilities...
The Design Utilities dialog appears.

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C Bus Interface
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C status and control interface to the ispClock5406D device. The I
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CMOS.
ispClock5400D Evaluation Board
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C pin header (Appendix A,
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C Design Utility.)
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User's Guide
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C interface fea-
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C