Lattice Semiconductor
5. Specify REF Frequency: 100 then click the Internal Feedback, Modify... button.
The External Feedback Setting dialog appears.
6. Select Internal Feedback, select Feedback taken from V-Divider 8, and click OK.
7. From the PLL Core Settings dialog, click OK.
8. From the Edit Symbol dialog, select USER PINS and click the Edit... button.
The USER Pin Function Allocation dialog appears.
9. Select PLL_BYPASS = PLL then click the OK button.
The USER Pin Summary dialog appears. Click the OK button.
10. From the Edit Symbol dialog select Output BANK_0 then click the Edit... button.
The Output Settings for BANK_0 & Bank_1 dialog appears.
11. Click the Source, Modify... button.
The Output Pair Source Setting dialog box appears.
12. For BANK_0, choose V-Divider-8, choose, From V-Divider, and click the OK button.
From the Output Settings for BANK_0 & BANK_1 dialog, select the following options for BANK_0:
Output Type: LVPECL
Output Enable: Always Enabled
Select the following option for BANK_1:
Output Enable: Always Disabled
Click the OK button.
13. From the Edit Symbol dialog select Output BANK_2 then click the Edit... button.
The Output Settings for BANK_2 & Bank_3 dialog appears.
14. From the Output Settings for BANK_2 & BANK_3 dialog, select the following options for BANK_2:
Output Enable: Always Disabled
Select the following option for BANK_3:
Output Enable: Always Disabled
Click the OK button.
15. From the Edit Symbol dialog select Output BANK_4 then click the Edit... button.
The Output Settings for BANK_4 & Bank_5 dialog appears.
16. From the Output Settings for BANK_4 & BANK_5 dialog, select the following options for BANK_4:
Output Enable: Always Disabled
Select the following option for BANK_5:
Output Enable: Always Disabled
Click the OK button.
17. From the Edit Symbol dialog, click Close.
18. Click the Download icon on the top toolbar.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
19. Click OK.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
ispClock5400D Evaluation Board
19
User's Guide