Lattice Semiconductor ispClock5400D User Manual page 11

Lattice Semiconductor
Figure 11. Scope Plot - Inverted Output Bank
6. Repeat steps 1-4 to adjust the output bank to not invert the output (Inverted = No) and reprogram the device.
Modify Clock Phase Skew
This section describes the procedure to modify phase skew of the ispClock5406D output. The Phase skew Unit
Delay (PUD) is 0.31 ns for the demo design. In the following procedure the phase skew will be advanced four PUD
units or 1.24 ns.
To modify clock phase skew:
1. From PAC-Designer choose Edit > Symbol...
The Edit Symbol dialog appears.
2. Choose Skew Manager and click the Edit... button
Phase Skew Manager appears.
3. Choose the following options:
Skew Step = Fine
BANK_2 Phase Skew = 4PUD
Click OK.
PAC-Designer updates the phase skew for the project.
4. Click the Download icon on the top toolbar.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
5. Click OK.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
6. Note the updated scope display.
ispClock5400D Evaluation Board
11
User's Guide