Plug And Play (Ddc 1 / 2) - NEC MultiSync FP1350 Service Manual

4) Plug and Play (DDC 1 / 2)

VESA Display Data Channels (DDC)
a. DDC1
When the monitor is turned on, the operation mode starts in DDC1 mode. When the VCLK (SYNC) is
provided to IC8A1 pin 7, serial data stream is generated from the IC8A1 pin 5 by synchronizing with the
rising edge of the VCLK. The contents of the serial data (SDA) is called EDID, and it contains the
information of monitor's specification and supported signals. The EDID is composed of 8 bits, 128 bytes,
but the individual data is composed of 9 bits. The 9th bit is always low and is ignored. If 128 bytes are
finished to generate, then the 24LCS21A starts to generate the first byte.
continuously until the operation mode changes to DDC2B.
SDA
VCLK
b. DDC2B
When the SCL (IC8A1 pin 6) input is changed from high to low, the operation mode changes from DDC1
to DDC2B. The output data is the same as DDC1 (EDID), but the communication protocol is different. In
DDC2B mode, the serial data is communicated by I
from DDC2B to DDC1 except by turning off the monitor.
SDA
SCL
VCLK
DDC1 mode
1 2 3 4 5 6 7 8 9
2
C-bus protocol. The operation mode never go back
8-25
This operation lasts
1 2
DDC2B mode