A12 Main Board - Tektronix MTX100A Service Manual

Theory of Operation

A12 Main Board

PCI Interface
Mega FIFO
TS Controller
MTX100A MPEG Recorder & Player Service Manual
This section describes the basic operation of the major circuit blocks or modules
in the MTX100A. The Diagrams section, beginning on page 6-1, includes a
block diagram and an interconnect diagram.
The A12 Main board consists of the following blocks:
The PCI interface consists of a PCI target and a PCI master. The PCI target has
three base address register areas. The PCI master has two DMA controllers used
to transfer data from the A12 Main board to the system memory or from the
system memory to the A12 Main board.
The Mega FIFO is a FIFO of each 32 M byte for playing and recording a stream
data. It consists of two 256 M bit synchronous DRAM and FPGA. This FIFO is
used to compensate for non-realtime operation of Windows XP.
The TS controller consists of the following blocks:
TS Packet Type Controller. This controller sets a packet size of 188, 204, 208, and
Non TS (free length) as a TS packet type. For a Non TS format, the controller
also sets a packet length (16-255) and data length (16-255). The data length
shows an effective data length in one TS packet.
Data Valid Controller. This block generates a data valid signal that synchronizes
with the first byte of a TS packet when stream output is started.
Psync Controller. Psync is a signal to identify the sync byte in a transport stream.
When the controller is not the Psync Regeneration mode, Psync is recognized as
the first byte of a transport stream. In this case, Psync is output in the constant
interval even when the sync byte is rewritten in the value except for 47h. For the
Super Frame mode, Psync is output only once in 384 packets.
Psync Regenerator. This block becomes active when the Psync Regeneration
mode is set. The block detects the sync byte (47h) in a data stream and regener-
ates a Psync signal. The psync generator supports 188, 204, 208 TS packets only.
2-1