Figure 4-3. Mvme2700 Interrupt Architecture - Motorola MVME2700 Series Installation And Use Manual

Interrupt Handling
The Raven ASIC, which controls PHB (PCI Host Bridge) MPU/local bus
interface functions on the MVME2700, performs interrupt handling as
well. Sources of interrupts may be any of the following:
The following figure illustrates interrupt architecture on the MVME2700.
For details on interrupt handling, refer to the MVME2600 Series Single
Board Computer Programmer's Reference Guide.
PIB
(8529 Pair)

Figure 4-3. MVME2700 Interrupt Architecture

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The Raven ASIC itself (timer or transfer error interrupts)
The processor (processor self-interrupts)
The Falcon chip set (memory error interrupts)
The PCI bus (interrupts from PCI devices)
The ISA bus (interrupts from ISA devices)
INT
RavenMPIC
SERR_& PERR_
PCI Interrupts
ISA Interrupts
Programming Considerations
INT_
Processor
MCP_
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