Calistoga 1/5 Host - EUROCOM M570U Service Manual

Schematic Diagrams

Calistoga 1/5 Host

Sheet 5 of 40
Layout Notice:
10 mils wide, 20 mils spacing
Calistoga 1/5 Host
+1.05VS
R336
R347
R335
R349
Layout Notice:
MCH_HXSWING and MCH_HYSWING
should be 10 mils traces
and 20 mils spacing
+1.05VS
R338
221_1%
R337
100_1%
B - 6 Calistoga 1/5 Host
U28A
[3] H_D#[63:0]
H_D#0 F1
H_D#_0
H_D#1 J1
H_D#_1
H_D#2 H1
H_D#_2
H_D#3 J6
H_D#_3
H_D#4 H3
H_D#_4
H_D#5 K2
H_D#_5
H_D#6 G1
H_D#_6
H_D#7 G2
H_D#_7
H_D#8 K9
H_D#_8
H_D#9 K1
H_D#_9
H_D#10 K7
H_D#_10
H_D#11 J8
H_D#_11
H_D#12 H4
H_D#_12
H_D#13 J3
H_D#_13
H_D#14 K11
H_D#_14
H_D#15 G4
H_D#_15
H_D#16 T10
H_D#_16
H_D#17 W11
H_D#_17
H_D#18 T3
H_D#_18
H_D#19 U7
H_D#_19
H_D#20 U9
H_D#_20
H_D#21 U11
H_D#_21
H_D#22 T11
H_D#_22
H_D#23 W9
H_D#_23
H_D#24 T1
H_D#_24
H_D#25 T8
H_D#_25
H_D#26 T4
H_D#_26
H_D#27 W7
H_D#_27
H_D#28 U5
H_D#_28
H_D#29 T9
H_D#_29
H_D#30 W6
H_D#_30
H_D#31 T5
H_D#_31
H_D#32 AB7
H_D#_32
H_D#33 AA9
H_D#_33
H_D#34 W4
H_D#_34
H_D#35 W3
H_D#_35
H_D#36 Y3
H_D#_36
54.9_1% MCH_HXSCOMP H_D#37 Y7
H_D#_37
H_D#38 W5
H_D#_38
54.9_1% MCH_HY SCOMP H_D#39 Y 10
H_D#_39
H_D#40 AB8
H_D#_40
24.9_1% MCH_HXRCOMP H_D#41 W2
H_D#_41
H_D#42 AA4
H_D#_42
24.9_1% MCH_HY RCOMP H_D#43 AA7
H_D#_43
H_D#44 AA2
H_D#_44
H_D#45 AA6
H_D#_45
H_D#46 AA10
H_D#_46
H_D#47 Y8
H_D#_47
H_D#48 AA1
H_D#_48
H_D#49 AB4
H_D#_49
H_D#50 AC9
H_D#_50
H_D#51 AB11
H_D#_51
H_D#52 AC11
H_D#_52
H_D#53 AB3
H_D#_53
H_D#54 AC2
H_D#_54
H_D#55 AD1
H_D#_55
H_D#56 AD9
H_D#_56
H_D#57 AC1
H_D#_57
+1.05VS
H_D#58 AD7
H_D#_58
H_D#59 AC6
H_D#_59
H_D#60 AB5
H_D#_60
H_D#61 AD10
H_D#_61
R346 H_D#62 AD4
H_D#_62
H_D#63 AC8
H_D#_63
221_1%
MCH_HXRCOMP E1
H_XRCOMP
MCH_HXSCOMP E2
H_XSCOMP
MCH_HXSWING E4
H_XSWING
MCH_HYRCOMP Y1
H_Y RCOMP
MCH_HYSCOMP U1
H_Y SCOMP
MCH_HYSWING W1
H_Y SWING
AG2
[2] CLK_MCH_BCLK
H_CLKIN
R348 C76 C553 AG1
[2] CLK_MCH_BCLK#
H_CLKIN#
100_1% 0.1UF_X7R 0.1UF_X7R
CALISTOGA
+1.05VS [3,4,6,8,9,13,16,29]
H_A#[31:3] [3]
H9 H_A#3
H_A#_3
C9 H_A#4
H_A#_4
E11 H_A#5
H_A#_5
G11 H_A#6
H_A#_6
F11 H_A#7
H_A#_7
G12 H_A#8
H_A#_8
F9 H_A#9
H_A#_9
H11 H_A#10
H_A#_10
J12 H_A#11
H_A#_11
G14 H_A#12
H_A#_12
D9 H_A#13
H_A#_13
J14 H_A#14
H_A#_14
H13 H_A#15
H_A#_15
J15 H_A#16
H_A#_16
F14 H_A#17
H_A#_17
D12 H_A#18
H_A#_18
A11 H_A#19
H_A#_19
C11 H_A#20 Layout Notice:
H_A#_20
A12 H_A#21
H_A#_21
A13 H_A#22 0.1uF should be placed
H_A#_22
E13 H_A#23
H_A#_23 100mils or less from GMCH
G13 H_A#24
H_A#_24
pin.
F12 H_A#25
H_A#_25
B12 H_A#26
H_A#_26
B14 H_A#27
H_A#_27
+1.05VS
C12 H_A#28
H_A#_28
A14 H_A#29
H_A#_29
C14 H_A#30
H_A#_30
D14 H_A#31
H_A#_31
R339
E8
H_ADS# [3]
H_ADS#
B9 100_1%
H_ADSTB#_0 H_ADSTB#0 [3]
C13
H_ADSTB#_1 H_ADSTB#1 [3]
J13 MCH_HLVREF
H_VREF_0
C6
H_BNR# H_BNR# [3]
F6 C80
H_BPRI# H_BPRI# [3]
C7 R340
H_BREQ#0 H_BR0# [3]
B7 0.1UF_X7R
H_CPURST# H_CPURST# [3]
A7 200_1%
H_DBSY # H_DBSY # [3]
C3
H_DEFER# H_DEFER# [3]
J9
H_DPWR# H_DPWR# [3]
H8
H_DRDY # H_DRDY # [3]
K13
H_VREF_1
J7
H_DINV#0 [3]
H_DINV#_0
W8
H_DINV#1 [3]
H_DINV#_1
U3
H_DINV#_2 H_DINV#2 [3]
AB10
H_DINV#3 [3]
H_DINV#_3
K4
H_DSTBN#0 [3]
H_DSTBN#_0
T7
H_DSTBN#1 [3]
H_DSTBN#_1
Y 5
H_DSTBN#2 [3]
H_DSTBN#_2
AC4
H_DSTBN#3 [3]
H_DSTBN#_3
K3
H_DSTBP#0 [3]
H_DSTBP#_0
T6
H_DSTBP#1 [3]
H_DSTBP#_1
AA5
H_DSTBP#_2 H_DSTBP#2 [3]
AC5
H_DSTBP#_3 H_DSTBP#3 [3]
D3
H_HIT# H_HIT# [3]
D4
H_HITM# H_HITM# [3]
B3
H_LOCK# H_LOCK# [3]
H_REQ#[4:0] [3]
D8 H_REQ#0
H_REQ#_0
G8 H_REQ#1
H_REQ#_1
B8 H_REQ#2
H_REQ#_2
F8 H_REQ#3
H_REQ#_3
A8 H_REQ#4
H_REQ#_4
B4
H_RS#0 [3]
H_RS#_0
E6
H_RS#1 [3]
H_RS#_1
D6
H_RS#2 [3]
H_RS#_2
E3
H_CPUSLP# [3]
H_SLPCPU#
E7
H_TRDY # [3]
H_TRDY #
BSEL2 BSEL1 BSEL0
1 0 1
0 0 1
0 1 1
1 1 1
+1.05VS
R325
1K/0402
R316 0/0402
[3] CPU_BSEL0 CLK_BSEL0 [2]
R317 *1K/0402 R324
1K/0402
MCH_BSEL0 [6]
+1.05VS
R323
1K/0402
R314 0/0402
[3] CPU_BSEL1 CLK_BSEL1 [2]
R315 *0/0402 R322
1K/0402
MCH_BSEL1 [6]
+1.05VS
R327
1K/0402
R318 0/0402
[3] CPU_BSEL2 CLK_BSEL2 [2]
R319 *0/0402 R326
Host Clock
1K/0402
Frequency
MCH_BSEL2 [6]
100 MHz
133 MHz
166 MHz
200 MHz