Table of Contents
Advertisement
3.7.6
Notes on Using Standby Mode
The CPU does not go to standby mode if an interrupt request occurs from a peripheral
function when a standby mode bit is set in the standby control register (STBC). Also, if
an interrupt is used to wake up from a standby mode to the normal operating state, the
operation after wake-up differs depending on whether or not the interrupt request is
accepted.
I Go to standby mode and interrupts
If an interrupt request with an interrupt level higher than "11
CPU, writing "1" to the stop bit (STP), sleep bit (SLP) in the standby control register (STBC) is ignored.
Therefore, the CPU does not go to standby mode (The CPU also does not go to the standby mode after
completing interrupt processing). This does not depend on whether or not the CPU accepts the interrupt.
Even if the CPU is currently performing interrupt processing, after clearing the interrupt request flag bit the
device can go to the standby mode if no other interrupt request is present.
I Wake-up from standby mode by interrupt
If an interrupt request with an interrupt level higher than "11
during sleep or stop mode, the CPU wakes up from standby mode. This does not depend on whether or not
the CPU accepts the interrupt.
After wake-up from standby mode, the CPU performs the normal interrupt operations. If the level set in the
interrupt level setting register (ILR1 to ILR3) corresponding to the interrupt request is higher than the
interrupt level bits in the condition code register (CCR: IL1, IL0), and if the interrupt enable flag is enabled
(CCR: I = "1"), the CPU branches to the interrupt processing routine. If the interrupt is not accepted,
operation restarts from the instruction following the instruction that activated the standby mode.
To prevent control from branching to an interrupt processing routine after wake-up, take measures such as
disabling interrupts before setting standby mode bit.
I Notes on setting standby mode
When setting the standby control register (STBC) to go to standby mode, make the settings in accordance
with Table 3.7-5 "Standby control register (STBC) low-power consumption mode settings". Although the
order of precedence as to which mode will be activated if more than one bit is set to "1" is stop mode and
sleep mode, it is best to set "1" for just one bit.
Table 3.7-5 Standby control register (STBC) low-power consumption mode settings
STP (Bit 7)
STBC register
SLP (Bit 6)
0
0
0
1
1
0
" occurs from a peripheral function to the
B
" occurs from a peripheral function or others
B
Mode
Normal
Sleep
Stop
CHAPTER 3 CPU
65
Advertisement
Table of Contents
