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3.4.2
Interrupt Processing
The interrupt controller transmits the interrupt level to the CPU when an interrupt
request is generated by a peripheral function. If the CPU is able to receive the interrupt,
the CPU temporarily halts the currently executing program and executes the interrupt
processing routine.
I Interrupt processing
The procedure for interrupt operation is performed in the following order: interrupt source generated at
peripheral function, set the interrupt request flag bit (request FF), discriminate the interrupt request enable
bit (enable FF), the interrupt level (ILR1, ILR2, ILR3 and CCR: IL1, IL0), simultaneously generated
interrupt requests with the same level, then check the interrupt enable flag (CCR: I). Figure 3.4-2 "Interrupt
processing" shows the interrupt processing.
(1)
request present at the
(2)
(7)
Figure 3.4-2 Interrupt processing
START
Initialize peripheral
Is an interrupt
YES
peripheral?
NO
Is interrupt
request output enabled
for the peripheral?
NO
(4)
Main program
execution
Interrupt processing routine
Restore PC and PS
Execute interrupt processing
Register
file
IR
IPLA
2
F
MC-8L CPU
(7)
(6)
RAM
Enable FF
AND
Request FF
(3)
Peripherals
YES
(3)
Check the interrupt priority level
and transfer the level to the CPU
Compare the level with
the IL bits in PS
YES
Is the level
higher than IL?
I-flag = 1?
NO
NO
Clear interrupt request
(6)
RETI
CHAPTER 3 CPU
Condition code
register (CCR)
PS
I
IL
Check
Comparator
(5)
Wake-up from
stop mode
Wake-up from
sleep mode
Exit watch mode
(4)
Interrupt
controller
(5)
YES
Save PC and PS to the stack
PC
interrupt vector
Update IL in PS
37
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