Port 4 Registers - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

I Block diagram of port 4 pins
PDR (Port data register)
PDR read
PDR read
(When Read-modify-write instruction executed)
PDR write
(Port data direction register)
DDR write
SPL: Pin state specification bit in the standby control register (STBC)
Reference:
Peripheral inputs continuously input the pin value (except during stop mode).
I Port 4 registers
The port 4 registers consist of PDR4 and DDR4.
Each bit in these registers has a one-to-one relationship with a port 4 bit and port 4 pin.
Table 4.6-2 "Correspondence between pin and register for port 4" shows the correspondence between pins
and registers for port 4.
Table 4.6-2 Correspondence between pin and register for port 4
Port
Port 4
Figure 4.6-1 Block diagram of port 4 pins
To external interrupt
To peripheral input
Peripheral output
Output latch
DDR
Stop mode (SPL = 1)
Correspondence between register bit and pin
PDR4 Bit 7
Corresponding pin --
DDR4 Bit 7
Corresponding pin --
External interrupt enable
Stop mode (SPL = 1)
Peripheral
output enable
Bit 6 Bit 5 Bit 4
P46 P45 P44
Bit 6 Bit 5 Bit 4
P46 P45 P44
CHAPTER 4 I/O PORTS
Pull-up resistor
Approx. 50 k
(Mask option)
P-ch
P-ch
Pin
N-ch
Bit 3 Bit 2 Bit 1
P43 P42 P41
Bit 3 Bit 2 Bit 1
P43 P42 P41
Bit 0
P40
Bit 0
P40
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