Appendix A I/O Map - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

APPENDIX

APPENDIX A I/O Map

Table A-1 "I/O map" lists the addresses of the registers of used by the internal
peripheral functions of the MB89950/950A series.
I I/O map
Table A-1 I/O map (1/2)
Address Register name
00 PDR0
H
01
H
02 PDR1
H
03
H
04 PDR2
H
05 to 07
H H
08 STBC
H
09 WDTC
H
0A TBTC
H
0B
H
0C PDR3
H
0D
H
0E PDR4
H
0F DDR4
H
10 to 11
H H
12 CNTR
H
13 COMR
H
14 PCR1
H
15 PCR2
H
16 RLBR
H
17 NCCR
H
18 to 1B
H H
1C SMR
H
264
Register description
Port 0 data register
Port 1 data register
Port 2 data register
Standby control register
Watchdog timer control register
Timebase timer control register
Port 3 data register
Port 4 data register
Port 4 direction register
PWM timer control register
PWM timer compare register
PWC pulse width control register 1
PWC pulse width control register 2
PWC reload buffer register
PWC noise filter control register
Serial mode register
Read/Write
(Vacancy)
(Vacancy)
(Vacancy)
(Vacancy)
(Vacancy)
(Vacancy)
(Vacancy)
Initial value
R/W 11111111
B
R/W 11111111
B
R/W --111111
B
R/W 0001----
B
W ----XXXX
B
R/W ---00000
B
R/W ----1111
B
R/W -XXXXXXX
W -0000000
B
R/W 0-000000
B
W XXXXXXXX
R/W 0-0--000
B
R/W 000-0000
B
R/W XXXXXXXX
R/W ------00
B
R/W 00000000
B
B
B
B