Clock Controller - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

3.6.2

Clock Controller

The clock controller contains the following four blocks:
• Main clock oscillator
• Clock controller
• Oscillation stabilization delay time selector
• Standby control register (STBC)
I Block diagram of clock controller
Figure 3.6-4 "Block diagram of clock controller" shows the block diagram of the clock controller.
Standby control register (STBC)
From timebase timer
F : Main clock oscillation frequency
CH
t : Instruction cycle (divide-by-four main clock oscillation)
inst
G
Main clock oscillator
The main clock oscillator is stopped in main stop mode.
Figure 3.6-4 Block diagram of clock controller
STBC STP SLP SPL RST
Enable
F
CH
Main clock
oscillator
14
2 /F
CH
Oscillation stabiliza-
tion delay time
selector (optional)
18
2 /F
CH
Mask option
— — — —
Divid e-by-2
Clock
Divi de-by-4
controller
Stop of supply to the CPU
CHAPTER 3 CPU
Pin state
Sleep mode
Stop mode
Clock for
timebase timer
Clock supply
to CPU
1 tinst
53