Fujitsu Semiconductor Controller MB89950/950A Hardware Manual page 205

G
Coding example
SMR EQU
SDR EQU
SIOF EQU
SST EQU
ILR2 EQU
INT_V DSEG
ORG
IRQ5 DW
INT_V ENDS
;-----Main program----------------------------------------------------------------
CSEG
:
CLRI
CLRB
MOV
MOV
MOV
SETB
SETI
:
;-----Interrupt processing routine------------------------------------------------
WARI CLRB
PUSHW
XCHW
PUSHW
MOV
SETB
:
User processing
:
POPW
XCHW
POPW
RETI
ENDS
;---------------------------------------------------------------------------------
END
001CH ; Serial mode register
001DH ; Serial data register
SMR:7 ; Define the interrupt request flag bit.
SMR:0 ; Define the serial I/O transfer start bit.
007DH ; Address of the interrupt level setting register 2
ABS ; [DATA SEGMENT]
0FFF0H
WARI ; Set interrupt vector.
; [CODE SEGMENT]
; Stack pointer (SP) etc. are already initialized.
; Disable interrupts.
SST ; Stop serial I/O transfer.
ILR2,#11110111B ; Set interrupt level (level 1).
SDR,#55H ; Set transfer data (55H).
SMR,#01111000B ; Clear Interrupt request flag, enable interrupt
; request output, enable shift clock output (SCK),
; enable serial data output (SO), select 32 tinst,
; LSB first.
SST ; Start serial I/O transfer.
; Enable interrupts.
SIOF ; Clear interrupt request flag.
A
A,T ; Save A and T.
A
SDR,#55H ; Reset transfer data (55H).
SST ; Start serial I/O transfer.
A
A,T ; Restore A and T
A
CHAPTER 9 8-BIT SERIAL I/O
191