Structure Of Uart - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

10.2

Structure of UART

The UART consists of the following blocks:
• Baud rate generator and serial clock generator
• Data transmitter and data receiver
• Registers (SMC1, SMC2, SRC, SSD, SIDR, SODR)
I Block diagram of UART
Baud rate generator and serial clock generator
UART serial clock
Serial I/O clock
1/4
1/6
CPU clock
1/13
1/65
PWM timer
output
P45/SCK
Data transmit control circuit
MC0
MC1
SBL
Timing
Transmitter
byte count
Reset
Data receive control circuit
P43/SI
Start bit
detection
CR
*1: At switching between port output and serial clock output, the SCKE bit of the UART is valid when the RSEL bit is 0; the SCKE bit of the serial I/O is
valid when the RSEL bit is 1.
*2: At switching between port output and serial data output, the SOE bit of the UART is valid when the RSEL bit is 0; the SOE bit of the serial I/O is
valid when the RSEL bit is 1.
Figure 10.2-1 Block diagram of UART
RSEL
1
SCKE*
P45/SCK
RC2
PDS1 CS1
RC1
PDS0
CS0
RC0
n
1/2
1/4
TDRE
Shifter
Shift clock
Transmitter
control
Transfer clock
SODR
MC1
MC0
Start Shift clock
Receiver
byte count
Transfer clock
Reset
ORFE
RDRF
Internal data bus
Registers:
SMC1 PEN SBL MC1
SMC2 — — PSEN
SSD RDRF ORFE TDRE
SRC — —
SODR
SIDR
CR
1/8
1/2
1/2
PEN TD8/TP
Parity
RSEL
generator
Serial I/O data
PEN
Parity
RD8/RP
generator
Shifter
SIDR
CHAPTER 10 UART
MC0 SMDE — SCKE
— — PDS1
RSEL
TIE RIE — TD8/TP RD8/RP
CR CS1 CS0 RC2 RC1
SMDE
Serial
clock
2
SOE*
P44/SO
TIE
TDRE
RIE
RDRF
ORFE
SOE
PDS0
RC0
IRQ4
199