Fujitsu Semiconductor Controller MB89950/950A Hardware Manual page 101

I Block diagram of port 3 pins
PDR (Port data register)
PDR read
PDR read (for bit manipulation instructions)
PDR write
SPL: Pin state specification bit in the standby control register (STBC)
Figure 4.5-2 Block diagram of port 3 pins (P32/V1 and P33/V2)
PDR (Port data register)
PDR read
PDR read (for bit manipulation instructions)
PDR write
SPL: Pin state specification bit in the standby control register (STBC)
Figure 4.5-1 Block diagram of port 3 pins (P30 and P31)
Output latch
Stop mode (SPL = 1)
Output latch
Stop mode (SPL = 1)
Stop mode (SPL = 1)
N-ch
PSEL bit of LCDR register
V1 or V2
N-ch
P-ch
Stop mode (SPL = 1)
N-ch
CHAPTER 4 I/O PORTS
Pin
Pin
87