Fujitsu Semiconductor Controller MB89950/950A Hardware Manual page 209

I Selection of transfer clocks
The transfer clock can selected from the external clock (SCK pin), PWM timer or dedicated baud rate
generator by setting CS0 and CS1 bits of serial rate control register (SRC). In addition, the CR bit of SRC
and SMDE bit of serial mode control register 1 (SMC1) can determine which divider for the selected
transfer clock. Please refer to Table 10.1-2 "Clock ratio".
Table 10.1-2 Clock ratio
CS1
0
0
1
1
When using the dedicated baud rate generator, the input clock of the baud rate generator is selected by
PDS1 and PDS0 bits of serial mode control register 2 (SMC2). The ratio of dividing frequency is shown in
Table 10.1-3 "Dividing frequency of dedicated baud rate generator".
Table 10.1-3 Dividing frequency of dedicated baud rate generator
PDS1
0
0
1
1
CS0 Clock input
0 External clock
1 PWM timer
0 Dedicated baud rate
generator
1
PDS0
0
1
0
1
CR
0
1
0
1
0
1
--
Dividing frequency
1/4
1/6
1/13
1/65
CHAPTER 10 UART
Asynchronous Synchronous
1/16
1/64
1/16
1/64
1/16
1/64
1/8
Input clock
CPU operating clock
CPU operating clock
CPU operating clock
CPU operating clock
1/1
1/2
1/2
1/1
195