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1.6.2 XceL4v dynamic server cache
The XceL4v dynamic server cache is a technology developed as part of the IBM
XA-64e fourth-generation chipset. It is used in two ways:
As a single four-way server, the XceL4v and its embedded DRAM (eDRAM) is
used as a snoop filter to reduce traffic on the front-side bus. It stores a
directory of all processor cache lines to minimize snoop traffic on the four
front-side buses and minimize cache misses.
When the x3950 M2 is configured as a multinode server, this technology
dynamically allocates 256 MB of main memory in each node for use as an L4
cache directory and scalability directory. This means an eight-way
configuration has 512 MB of XceL4v cache.
Used in conjunction with the XceL4v Dynamic Server Cache is an embedded
DRAM (eDRAM), which in single-node configurations contains the snoop filter
lookup tables. In a multinode configuration, this eDRAM contains the L4 cache
directory and the scalability directory.
Note: The amount of memory that BIOS reports is minus the portion used for
the XceL4v cache.
1.6.3 PCI Express I/O bridge chip
Two single-chip PCIe host bridges are designed to support PCIe adapters for
IBM x3850 M2 and x3950 M2 servers. The PCIe bridges each have one HSS-IB
port that provide connectivity to Hurricane 4 memory controller chip and also
another HSS-IB link between the PCIe bridges for redundancy in the event one of
the links from the Hurricane 4 chipset to the two PCIe bridges are not working.
The HSS-IB links are capable of up to 3.0 GBps bandwidth in each direction per
port or up to 6.0 GBps bidirectional bandwidth (see Figure 1-12 on page 28).
Each PCIe chip provides four separate PCIe x8 buses to support four PCIe x8
slots. PCIe Bridge 1 supports slots 1-4 of the PCIe x8 slots and PCIe Bridge 2
supports slots 5-7 of the PCIe x8 slots and a dedicated PCIe x8 slot for
ServeRAID MR10k SAS/SATA RAID controller.
1.6.4 High-speed memory buffer chips
The two high-speed memory buffer chips on each memory card are used to
extended memory capacity. They provide the necessary functions to connect up
to 32 8-byte ranks of DDR-II memory (see 1.6.5, "Ranks" on page 31 for an
explanation of ranks of memory). Each buffer supports multiple data flow modes
30
Planning, Installing, and Managing the IBM System x3950 M2
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