IBM 88743BU - System x3950 E User Manual page 110

Table 3-2 contains the processor options supported in the x3850 M2 and x3950
M2 (machine type 7233) with Xeon 7400
processor option includes a CPU, heat-sink, and VRM.
Table 3-2 Dunnington processor options for x3950 M2 and x3850 M2: machine type 7233
Processor Cores
Xeon L7445 4-core
Xeon E7420 4-core
Xeon E7430 4-core
Xeon E7440 4-core
Xeon L7455 6-core
Xeon E7450 6-core
Xeon X7460 6-core
a. For a description of TDP, see footnote a in Table 3-1.
b. The first feature code is the base configuration. Additional processor orders should use the second
feature code.
Note: The x3950 M2 and x3850 M2 models with Xeon 7200 and 7300
Tigerton
installation of Xeon 7400
Processor cache: Tigerton
The Intel Xeon 7200 and 7300 series processors (Tigerton) have two levels of
cache on the processor die:
L1 cache
L2 cache
L3 cache
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Planning, Installing, and Managing the IBM System x3950 M2
Speed L2 / L3 cache
2.13 GHz 2x3 /12 MB
2.13 GHz 2x3 /12 MB
2.13 GHz 2x3 /12 MB
2.4 GHz 2x3 /12 MB
2.13 GHz 3x3 /16 MB
2.4 GHz 3x3 /16 MB
2.67 GHz 3x3 /16 MB
processors (machine types 7141/7144) do not support the
Dunnington
The L1 execution, 32 KB instruction and 32 KB data, for data trace
cache in each core is used to store micro-operations, which are
decoded executable machine instructions. It serves those to the
processor at rated speed. This additional level of cache saves
decoding time on cache hits.
Each pair of cores in the processor has either 2 MB, 3 MB, or 4 MB
of shared L2 cache, for a total of 4 MB, 6 MB, or 8 MB of L2 cache.
The L2 cache implements the Advanced Transfer Cache
technology.
Tigerton processors do not have L3 cache.
Dunnington
processors. Each
a
TDP Part number
50 W 44E4517
90 W 44E4469
90 W 44E4470
90 W 44E4471
65 W 44E4468
90 W 44E4472
130 W 44E4473
processors.
b
Feature code
6976 / 4435
3647 / 4419
3648 / 4420
3646 / 4418
3645 / 4417
3649 / 4421
3644 / 4416