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Note: This function is only used for 32-bit operating environments where the
processor is in one of the following modes:
Legacy protected mode, if Physical Address Extension (PAE) is enabled on
a 32-bit operating system.
IA-32e mode, when EM64T is enabled on a 64-bit operating system.
The operating system must also implement this function.
The XD feature is implemented in Linux OS as Data Execution Prevention
(DEP) and Windows OS as Execute Disable Bit (EDB).
For more details of the Execute Disable Bit function, see:
http://www.intel.com/technology/xdbit/index.htm
Intel Virtualization Technology
To reduce the complexity of the hypervisor, which can reduce overhead and
improve performance significantly, enable (default) this setting, if it is not already.
Processor IP Prefetcher
The purpose of the IP prefetcher, as with any prefetcher, is to predict what
memory addresses will be used by the program and deliver that data just in time.
To improve the accuracy of the prediction, the IP prefetcher tags the history of
each load using the Instruction Pointer (IP) of the load. For each load with an IP,
the IP prefetcher builds a history and keeps it in the IP history array. Based on
load history, the IP prefetcher tries to predict the address of the next load
according to a constant stride calculation (a fixed distance or
subsequent accesses to the same memory area).
The IP prefetcher then generates a prefetch request with the predicted address
and brings the resulting data to the Level 1 data cache.
This setting is disabled by IBM (the opposite of the Intel default). The
observations in the IBM performance lab have shown that this prefetcher is
negligible in most real applications. Although Intel recommends that the
Processor Hardware Prefetcher option be enabled for some server workloads
similar to the Streams benchmark, the actual setting should be determined by
performance testing in your intended workload environment.
stride
Chapter 3. Hardware configuration
between
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