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L2 cache
Figure 1-16 Block diagram of Dunnington 6-core processor package
Key features of the processors used in the x3850 M2 and x3950 M2 include:
Multi-core processors
The Tigerton dual-core processors are a concept similar to a two-way SMP
system except that the two processors, or
silicon die. This brings the benefits of two-way SMP with lower software
licensing costs for application software that licensed per CPU socket plus the
additional benefit of less processor power consumption and faster data
throughput between the two cores. To keep power consumption down, the
resulting core frequency is lower, but the additional processing capacity
means an overall gain in performance.
The Tigerton quad-core processors add two more cores onto the same die,
and some Dunnington processors also add two more. Hyper-Threading
Technology is not supported.
Each core has separate L1 instruction and data caches, and separate
execution units (integer, floating point, and so on), registers, issue ports, and
pipelines for each core. A multi-core processor achieves more parallelism
than Hyper-Threading Technology because these resources are not shared
between the two cores.
With two times, four times, and even six times the number of cores for the
same number of sockets, it is even more important that the memory
subsystem is able to meet the demand for data throughput. The 34.1 GBps
peak throughput of the x3850 M2 and x3950 M2's eX4 technology with four
memory cards is well suited to dual-core and quad-core processors.
36
Planning, Installing, and Managing the IBM System x3950 M2
6-core Xeon E7400
(Code name: Dunnington)
L2 cache
L2 cache
L3 cache
cores
, are integrated into one
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