Timestamp Clock Event - Intel X38ML - Server Board Motherboard Technical Manual

Error Reporting and Handling
Field
Sensor Type See the Intelligent Platform
Management Interface Specification,
Version 2.0.
Sensor The number of the sensor that
Number generated this event.
Type Code 0x6F if event offsets are specific to
the sensor.
Event Data 1 7:6
00 = Unspecified byte 2
10 = OEM code in byte 2
5:4
00 = Unspecified byte 3
10 = OEM code in byte 3.
The BIOS will not use encodings
01 and 11 for errors discussed in
this document.
3:0 Offset from Event Trigger for
discrete event state.
Event Data 2 7:0 OEM code 2 or unspecified.
Event Data 3 7:0 OEM code 3 or unspecified.
6.2.4

Timestamp Clock Event

The BMC maintains a 4-byte internal timestamp clock used by the SEL and SDR subsystems.
This clock is incremented once per second and is read and set using the Get SEL Time and Set
SEL Time commands. You can also use the Get SDR Time command to read the timestamp
clock. These commands are specified in the Intelligent Platform Management Interface
Specification, Version 2.0.
6.2.4.1 No Real-Time Clock (RTC) Access
After a BMC reset, the BMC sets the initial value of the timestamp clock to 0x00000000. It is
incremented once per second after that. A SEL event containing a timestamp from 0x00000000
to 0x14000000 has a timestamp value that is relative to BMC initialization.
During POST, the BIOS tells the BMC the current RTC time via the Set SEL Time command.
The BMC maintains that time using a hardware signal driven from the same oscillator that
maintains the system's time-of-day clock. The BIOS sends a Timestamp Clock Sync System
event immediately before and immediately after the Set SEL Time command. The following
table describes the event format.
96
IPMI Definition
Intel order number E15331-006
BIOS Implementation
reserved.
0
1 = ID is system software ID.
As a result, the generator ID byte will start from 0x31 and
go up to 0x3F, in increments of 2 for events logged by the
BIOS.
0Fh – System Firmware Progress (formerly POST Error)
06h – POST Error (BIOS)
0x6F
If event data 2 and event data 3 contain OEM codes, bits
7:6 and bits 5:4 contain 10. For platforms that do not
include the POST code information with FRB-2 log, both of
these fields are 0. BIOS should either specify both bytes or
should mark both bytes as unspecified. Data 1 = 0A0h.
Data 2 and Data 3 each contain part of the 'Watchdog timer
failed on last boot' error code 8190. Data 2 = 090h.
Data 2 and Data 3 each contain part of the 'Watchdog timer
failed on last boot' error code 8190. Data 3 = 081h.
Intel® Server Board X38ML
Revision 1.3