Table 24. Agp Connector - Intel S875WP1LX Specification

Connectors and Jumper Blocks
Pin Signal Name
A24 Ground
A25 AD24
A26 IDSEL
A27 +3.3 V
A28 AD22
A29 AD20
A30 Ground
A31 AD18
Note:
1. The signals (in parentheses) are optional in the PCI specification and are not currently implemented.
2. On PCI Slot 3, A9 becomes P_REQ5#
3. On PCI Slot 3, B10 becomes P_GNT5#
4. On PCI Slot 3, B14 becomes CK_P_33M_S3_RISER
5.3 AGP Connector
Pin Signal Name
A1 +12 V
A2 TYPEDET#
A3 Reserved
A4 Not connected
A5 Ground
A6 INTA#
A7 RST#
A8 GNT1#
A9 Vcc3.3
A10 ST1
A11 Reserved
A12 PIPE#
A13 Ground
A14 WBF#
A15 SBA1
A16 Vcc3.3
A17 SBA3
A18 SBSTB#
A19 Ground
A20 SBA5
A21 SBA7
A22 Reserved
A23 Ground
A24 Reserved
42
Pin Signal Name
B24 AD25
B25 +3.3 V
B26 C/BE3#
B27 AD23
B28 Ground
B29 AD21
B30 AD19
B31 +3.3 V

Table 24. AGP Connector

Pin Signal Name Pin
B1 Not connected A34
B2 +5 V A35
B3 +5 V A36
B4 Not connected A37
B5 Ground A38
B6 INTB# A39
B7 CLK A40
B8 REQ# A41
B9 Vcc3.3 A42
B10 ST0 A43
B11 ST2 A44
B12 RBF# A45
B13 Ground A46
B14 Reserved A47
B15 SBA0 A48
B16 Vcc3.3 A49
B17 SBA2 A50
B18 SB_STB A51
B19 Ground A52
B20 SBA4 A53
B21 SBA6 A54
B22 Reserved A55
B23 Ground A56
B24 +3.3 V (aux) A57
Pin Signal Name Pin
A55 AD04 B55
A56 Ground B56
A57 AD02 B57
A58 AD00 B58
A59 +5 V (I/O) B59
A60 REQ64# B60
A61 +5 V B61
A62 +5 V B62
Signal Name Pin Signal Name
Vddq B34 Vddq
AD22 B35 AD21
AD20 B36 AD19
Ground B37 Ground
AD18 B38 AD17
AD16 B39 C/BE2#
Vddq B40 Vddq
FRAME# B41 IRDY#
Reserved B42 +3.3 V (aux)
Ground B43 Ground
Reserved B44 Reserved
Vcc3.3 B45 Vcc3.3
TRDY# B46 DEVSEL#
STOP# B47 Vddq
PME# B48 PERR#
Ground B49 Ground
PAR B50 SERR#
AD15 B51 C/BE1#
Vddq B52 Vddq
AD13 B53 AD14
AD11 B54 AD12
Ground B55 Ground
AD9 B56 AD10
C/BE0# B57 AD8
S875WP1-E TPS
Signal Name
AD05
AD03
Ground
AD01
+5 V (I/O)
ACK64#
+5 V
+5 V
Revision 4.0