Table 8. Fan Connector Function/Operation - Intel S875WP1LX Specification

S875WP1-E TPS
3.6.2.2 Fan Connectors
CAUTION
The processor fan must be connected to the processor fan connector, not to a chassis fan
connector. Connecting the processor fan to a chassis fan connector may result in onboard
component damage that will halt fan operation.
Table 8 summarizes the fan connector function/operation.
Connector
• +12 V DC connection for a processor fan or active fan heatsink.
Processor fan
• Fan is on in the S0 or S1 state.
• Wired to a fan tachometer input of the hardware monitoring and fan control ASIC.
• Closed-loop fan control that can adjust the fan speed or switch the fan on or off as
• +12 V DC connection for a system or chassis fan.
System fans
• Fan is on in the S0 or S1 state.
• Wired to a fan tachometer input of the hardware monitoring and fan control ASIC.
• Closed-loop fan control that can adjust the fan speed or switch the fan on or off as
For information about:
The location of the fan connectors
The signal names of the fan connectors
3.6.2.3 LAN Wake Capabilities
CAUTION
For LAN wake capabilities, the +5 V standby from the power supply must be capable of
providing adequate +5 V standby current. Failure to provide adequate standby current when
implementing LAN wake capabilities can damage the power supply.
LAN wake capabilities enable remote wake-up of the computer through a network. The LAN
subsystem PCI bus network adapter monitors network traffic at the Media Independent
Interface. Upon detecting a Magic Packet* frame, the LAN subsystem asserts a wake-up signal
that powers up the computer. Depending on the LAN implementation, the server board
S875WP1-E supports LAN wake capabilities with ACPI in the following ways:
23 PCI bus PME# signal for PCI 2.2 compliant LAN designs
•
Onboard LAN subsystem
Revision 4.0

Table 8. Fan Connector Function/Operation

Fan is off when the system is off or in the S3, S4, or S5 state.
needed.
Fan is off when the system is off or in the S3, S4, or S5 state.
needed.
Functional Architecture
Description
Refer to:
Figure 1
Section 5.13.1
27