Intel 875P Chipset; Figure 6. Intel 875P Chipset Block Diagram - Intel S875WP1LX Specification

S875WP1-E TPS
3.2

Intel 875P Chipset

The Intel 875P chipset consists of the following devices:
•
Intel 82875P Memory Controller Hub (MCH) with Accelerated Hub Architecture (AHA)
bus
•
Intel 82801ER I/O Controller Hub (ICH5-R) with AHA bus
•
Intel 82802AC (8 Mbit) Firmware Hub (FWH)
The MCH is a centralized controller for the system bus, the memory bus, the AGP bus, and the
Accelerated Hub Architecture interface. The ICH5-R is a centralized controller for the Server
Board S875WP1-E's I/O paths. The FWH provides the nonvolatile storage of the BIOS. The
component combination provides the chipset interfaces as shown in Figure 6.
System Bus
82875P
Memory Controller
Hub (MCH)
Dual-Channel
AGP
DDR SDRAM
Interface
For information about
The Intel 875P chipset
Revision 4.0
UDMA 33
ATA-66/100
875P Chipset
82801ER
AHA
I/O Controller Hub
Bus
(ICH5-R)
SATA
SMBus
Ports
Bus

Figure 6. Intel 875P Chipset Block Diagram

Functional Architecture
Network
USB
82802AC
8 Mbit Firmware
Hub (FWH)
LPC Bus
PCI
AC Link
Bus
Refer to
http://developer.intel.com
OM15967
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