Error Sources And Types; Pci Bus Errors; Processor Bus Errors - Intel S875WP1LX Specification

Error Reporting and Handling
8. Error Reporting and Handling
This section documents the types of system bus error conditions monitored by the Intel Server Board
S875WP1-E.
8.1

Error Sources and Types

One of the major requirements of server management is to correctly and consistently handle
system errors. System errors, which can be disabled and enabled individually or as a group, can
be categorized as follows:
71 PCI bus
72 Memory single- and multi-bit errors
73 Sensors
74 Processor internal errors, bus/address errors, thermal trip errors, temperatures and
voltages, and GTL voltage levels
•
Errors detected during POST, logged as 'POST errors'
On the S875WP1-E platform, the Heceta chip manages general hardware monitoring sensors
on a hardware level; however action is only taken by software (i.e., an application such as
LANDesk™ Client Manager).
8.1.1

PCI Bus Errors

The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction, or to report it using SERR#. All other PCI-related errors are reported
by SERR#. SERR# is routed to NMI if enabled by BIOS.
8.1.2

Processor Bus Errors

The MCH supports the data integrity features supported by the Pentium® Pro bus, including
address, request, and response parity. The 875P chipset always generates ECC data while it is
driving the processor data bus, although the data bus ECC can be disabled or enabled by BIOS.
It is enabled by default.
86
S875WP1-E TPS
Revision 4.0