System Unit Functional Block Diagram - HP Visualize J5000 - Workstation Service Handbook

Processor Module
PCX–T"
CPU
and
CACHE
64
MASTER
MEMORY
CONTROLLER
432 PGA
39 @ 60MHz
SLAVE ADDRESS BUS
Control B
Control A
144 @ 30 MHz
Slave
72b SIMM
Memory
Controller
72b SIMM
208
MQUAD
Slave
72b SIMM
Memory
Controller
72b SIMM
208
MQUAD
Slave
Memory
Controller
208
MQUAD
Slave
Memory
Controller
208
MQUAD
16–SLOT
MEMORY INTERFACE
1 GB (16 mbit DRAM)
Double height SIMM
Figure 6–2. System Unit Functional Block Diagram
6–4 Diagrams
Processor Module
PCX–T"
CPU
and
CACHE
64
GSC+
INTERFACE
432 PGA
Chips
4x(160 POFP)
40 MHZ
GSC+
72 @ 30MHz
72b SIMM
72b SIMM
CORE I/O
72b SIMM
72b SIMM
32
72b SIMM 72b SIMM
FWSCSI
72b SIMM 72b SIMM
72b SIMM 72b SIMM
72b SIMM 72b SIMM
SYSTEM
CLOCK
System
SOURCE
Motherboard
PDC
EEPROM
U2 PDH
40 MHz
GSC+
GRAPHICS
3 GSC+
Card Slots
Config Reg
SE SCSI–2
802.3 LAN
2–PS2
RS323
Centronics
CD–Audio
32
HIL
EISA
INTERFACE
RS232
32
4 EISA
Card Slots
EISA PCA