Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 64

Workaround: Software must be written to ensure that the RLP has woken-up in response to
GETSEC[WAKEUP] instruction and then execute GETSEC[ENTERACCS]
instruction.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI115. Instruction Fetch May Cause a Livelock During Snoops of the L1 Data
Cache
A livelock may be observed in rare conditions when instruction fetch causes
Problem:
multiple level one data cache snoops.
Implication: Due to this erratum, a livelock may occur. Intel has not observed this
erratum with any commercially available software.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI116. Use of Memory Aliasing with Inconsistent Memory Type may Cause a
System Hang or a Machine Check Exception
Software that implements memory aliasing by having more than one linear
Problem:
addresses mapped to the same physical page with different cache types may
cause the system to hang or to report a machine check exception (MCE). This
would occur if one of the addresses is non-cacheable and used in a code
segment and the other is a cacheable address. If the cacheable address finds
its way into the instruction cache, and the non-cacheable address is fetched
in the IFU, the processor may invalidate the non-cacheable address from the
fetch unit. Any micro-architectural event that causes instruction restart will
be expecting this instruction to still be in the fetch unit and lack of it will
cause a system hang or an MCE.
Implication: This erratum has not been observed with commercially available software.
Workaround: Although it is possible to have a single physical page mapped by two different
linear addresses with different memory types, Intel has strongly discouraged
this practice as it may lead to undefined results. Software that needs to
implement memory aliasing should manage the memory type consistency.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI117. A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
Under certain conditions, as described in the Software Developers Manual
Problem:
section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon,
and P6 Family Processors", the processor may perform REP MOVS or REP
STOS as write combining stores (referred to as "fast strings") for optimal
performance. FXSAVE may also be internally implemented using write
combining stores. Due to this erratum, stores of a WB (write back) memory
64 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata