Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 53

Errata
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count
higher than expected.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI85. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
The ENTER instruction is used to create a procedure stack frame. Due to this
Problem:
erratum, if execution of the ENTER instruction results in a fault, the dynamic
storage area of the resultant stack frame may contain unexpected values (i.e.
residual stack data as a result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the
ENTER instruction. Please refer to "Procedure Calls For Block-Structured
Languages" in IA-32 Intel
Basic Architecture, for information on the usage of the ENTER instructions.
This erratum is not expected to occur in ring 3. Faults are usually processed
in ring 0 and stack switch occurs when transferring to ring 0. Intel has not
observed this erratum on any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI86. CPUID Reports Architectural Performance Monitoring Version 2 is
Supported, When Only Version 1 Capabilities are Available
CPUID leaf 0Ah reports the architectural performance monitoring version that
Problem:
is available in EAX[7:0]. Due to this erratum CPUID reports the supported
version as 2 instead of 1.
Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in
comparison to which features are actually supported.
Workaround: Software should use the recommended enumeration mechanism described in
the Architectural Performance Monitoring section of the Intel
Architectures Software Developer's Manual, Volume 3: System Programming
Guide.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI87. Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
When an unaligned access is performed on paging structure entries,
Problem:
accessing a portion of two different entries simultaneously, the processor
may live lock.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
®
Architecture Software Developer's Manual, Vol. 1,
®
64 and IA-32
53