Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 62

the physical APIC access page to avoid such an overlap. Under normal
circumstances for correctly written software, such an overlap is not expected
to exist. Intel has not observed this erratum with any commercially available
software.
Workaround: For a fully comprehensive workaround, the VMM should not allow the logging
of branch or PEBS records while guest software is running if the "virtualize
APIC accesses" VM-execution control is 1.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI110. VTPR Write Access During Event Delivery May Cause an APIC-Access
VM Exit
VTPR write accesses should not cause APIC-access VM exits but instead
Problem:
should cause data to be written to the virtual-APIC page. Due to this
erratum, a VTPR write access during event delivery may cause an APIC-
access VM exit with no data being written to the virtual-APIC page.
Implication: VTPR accesses are accesses to offset 80H on the APIC-access page. VTPR
write accesses can occur during event delivery when pushing data on the
stack. Because event delivery performs multiple stack pushes, an event
delivery that includes a VTPR write access will also include at least one other
write to the APIC-access page. That other write will cause an APIC-access
VM exit. Thus, even in the presence of this erratum, any event delivery that
includes a VTPR write access will cause an APIC-access VM exit. The only
difference with respect to correct behavior will be with regard to page offset
saved in the exit qualification by the APIC-access VM exit. A VMM should be
able to emulate the event delivery correctly even with the incorrect offset.
Workaround: The VMM should emulate any event delivery that causes an APIC-access VM
exit in the same way regardless of the offset saved in the exit qualification.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI111. BIST Failure After Reset
The processor may show an erroneous BIST (built-in self test) result in bit
Problem:
[17] of EAX register when coming out of reset.
Implication: When this erratum occurs, an erroneous BIST failure will be reported in EAX
bit [17]. This failure can be ignored since it is not accurate.
Workaround: It is possible for BIOS to workaround this erratum by masking off bit [17] of
the EAX register after coming out of reset.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI112. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
62 Intel
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
®
Core™2 Extreme Processor X6800 and
Specification Update
Errata