Intel CORE 2 DUO E4000 - SPECIFICATION UPDATE 3-2008 Specification page 59

Errata
AI101. (E)CX May Get Incorrectly Updated When Performing Fast String REP
STOS With Large Data Structures
When performing Fast String REP STOS commands with data structures
Problem:
[(E)CX*Data Size] larger than the supported address size structure (64K for
16-bit address size and 4G for 32-bit address size) some addresses may be
processed more than once. After an amount of data greater than or equal to
the address size structure has been processed, external events (such as
interrupts) will cause the (E)CX registers to be incremented by a value that
corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit
address size.
Implication: (E)CX may contain an incorrect count which may cause some of the STOS
operations to re-execute. Intel has not observed this erratum with any
commercially available software.
Workaround: Do not use values in (E)CX that when multiplied by the data size give values
larger than the address space size (64K for 16-bit address size and 4G for
32-bit address size).
For the steppings affected, see the Summary Tables of Changes.
Status:
AI102. Performance Monitoring Event BR_INST_RETIRED May Count CPUID
Instructions as Branches
Performance monitoring event BR_INST_RETIRED (C4H) counts retired
Problem:
branch instructions. Due to this erratum, two of its sub-events mistakenly
count for CPUID instructions as well. Those sub events are:
BR_INST_RETIRED.PRED_NOT_TAKEN (Umask 01H) and
BR_INST_RETIRED.ANY (Umask 00H).
Implication: The count value returned by the performance monitoring event
BR_INST_RETIRED.PRED_NOT_TAKEN or BR_INST_RETIRED.ANY may be
higher than expected. The extent of over counting depends on the occurrence
of CPUID instructions, while the counter is active.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI103. Performance Monitoring Event MISALIGN_MEM_REF May Over Count
Performance monitoring event MISALIGN_MEM_REF (05H) is used to count
Problem:
the number of memory accesses that cross an 8-byte boundary and are
blocked until retirement. Due to this erratum, the performance monitoring
event MISALIGN_MEM_REF also counts other memory accesses.
Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The
extent of over counting depends on the number of memory accesses retiring
while the counter is active.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
59